Level VSI Research Articles

A Novel Method to Eliminate Negative Time Period of SVPWM using DSP TMS320F2812

Conventional SVPWM method generates negative time period during lower switching frequency at higher voltage magnitudes. This paper presents a simplified method for implementation of Space Vector PWM technique for two level VSI using DSP TMS320F2812. Methodology presented is to implement SVPWM without lookup table and to calculate time periods independent of voltage magnitude. Experimental results show that proposed method overcomes problem of negative time period for said conditions. An experimental setup is developed in the laboratory around TMS320F2812 to obtain and verify the desired results. This work is a part of project titled “Development of FPGA-DSP Controlled Multilevel Inverter Interface for Grid connection of Wind Turbine Generators” funded by AICTE New Delhi.

Advanced hybrid SVPWM techniques for two level VSI

ABSTRACT This paper brings an advanced class of hybrid SVPWM techniques for medium voltage drive applications with two-level inverter which employs multiple division of active vector time (MDAVT) switching sequences to reduce total harmonic distortion (THD) and switching loss. The proposed hybrid SVPWM techniques are categorised based on the principle of bus-clamping strategies. Multiple division active vector time (MDAVT) switching sequences are used in the proposed strategies. The newly developed MDAVT switching strategies produce PWM waveform for all odd and even pulse number and maintain the symmetry of the voltage waveform. This work compares different MDAVT switching sequences based on modulation index and location of the clamping position (zero vector changing angle) of a phase in a line cycle. The proposed techniques lead to the reduction in weighted total harmonic distortion of line voltage (Vwthd) as well as switching loss. The results point to the superior order of performance of the developed MDAVT sequences in the various ranges of operation of modulation index and power factor values. The superior harmonic performance and switching loss characteristics of the MDAVT PWM techniques over the conventional SVPWM is experimentally verifiedona415 V, 2 hp induction motor drive.

Controlled diode bridge clamped three level Z source inverter and its PWM control

ABSTRACT Controlled Diode Bridge Clamped (CDBC) three level inverter configuration is the optimized version of T-type voltage source inverter in terms of power switches and their associated gate driver components. After a brief introduction of CDBC VSI, this paper implements the concept of Z-source inverter into this configuration. The three level SVPWM technique has been used for the generation of gating pulses. It has been pointed out that, in contrast to three level VSI, the switching frequency of three level ZSI depends on the modulation index for any particular carrier frequency. Also, a new switching state pattern has been suggested for optimizing the switching frequency of the power switches using max constant boost (MCB) and simple boost control (SBC) approach of voltage boosting. Comparing the same category of MCB or SBC control, the proposed switching pattern offers minimum switching frequency of power switches without affecting total harmonic distortion of line voltage/current as compared to the existing PWM switching patterns of three level ZSI. The condition of nearest three vector switching has been followed to ensure better output waveform quality. Simulation and experimental results verify the proposed inverter configuration and its PWM technique.

PWM Technique for Single Phase Asymmetrical Hybrid Multilevel Inverter for Non-linear and Dynamic loads

A two level VSI has output voltage either equal to positive or negative source voltage. This inverter has more ripple. In order to reduce the ripple content more number of switches are needed to produce many number of stepped voltage waveform. This improves the quality of power. This switching losses depends on the frequency of operation so when a two level inverter is operated at high frequency, the switching losses are predominant. This limits the use of such inverters. Hence, being replaced by Multilevel inverters. They have attracted academician and industry personal for medium and high-power power control. Such attractive features are available in hybrid multilevel inverter. Hence, these are preferred. They provide multi-level operation by using hybrid sources. Moreover, the number of power electronics components needed are less than conventional CMI for same voltage level. Thus, such inverters have more efficiency. In the proposed techniques, an asymmetrical hybrid multilevel inverter has been simulated using MATLAB Simulink. The results obtained have been presented for three different types of load.

Modified SVPWM Algorithm for Three Level VSI With Synchronized and Symmetrical Waveforms

To generate the required reference vector than triangle comparison based PWM techniques for three-level inverters the space vector based PWM (SVPWM) strategies contain broader choice of switching sequences. This space vector based PWM technique involves in various steps. These steps are computationally exhaustive. The SVPWM has been used in three phase inverter control system. The center-aligned PWM is the most effective way for the Microprocessor Control Unit implementation of the SVPWM, because it can easily generate the center aligned PWM of the multilevel inverters for generation of the signal of space vector pulse width modulation (SVPWM), this concept brings out the method. The inverter leg switching times are generated by this algorithm and middle vector switching times are centered in a sampled interval. The proposed algorithm does not require any sector identification. And it reduces the computational time as a result. The adjacent voltage space vectors are forming the small triangles it is called sectors. Multilevel converters can meet the increasing demand of power ratings and power quality associated with reduced harmonic distortion and lower electromagnetic interference. Furthermore to optimize switching waveforms, space vector pulse-width modulation algorithms offer great flexibility among them. Finally the results are verified through MATLAB/SIMULINK

A Novel Approach for Space Vector Based PWM Algorithm for Diode Clamped Three level VSI Fed Induction Motor Drive

<p>Performance of a voltage source inverter depends on pulse width modulation algorithms. Various algorithms exist for conventional space vector as well as space vector based bus clamped pulse width modulation for multilevel inverter in the literature. In this paper appropriate region selection algorithm for conventional space vector pulse width modulation (CSVPWM) and bus clamped pulse width modulation (BCPWM) techniques are proposed for diode clamped three level voltage source inverter. The proposed techniques are implemented on a three level voltage source inverter fed induction motor drive for open loop operation. The schemes are simulated in MATLAB/SIMULINK environments. The merit of proposed region selection algorithm is tested and verified through simulation result. Further performance comparisons between SVPWM and BCPWM for different modulation index are discussed. </p>

Performance Comparison of Multilevel Inverter Topologies for Closed Loop v/f Controlled Induction Motor Drive

This work focuses on investigating the closed loop model of Multilevel inverter fed Induction Motor Drive with constant V/f method. Multi level inverter generates stepped sinusoidal waveforms of lower harmonics with increasing levels. Cascaded MLI of 5 level and conventional VSI are synthesized using sinusoidal pulse width modulation (SPWM). The multi level inverter output so developed assuring the least THD is then passed through a filter to get a better sinusoid output. The filtered output is then fed to the induction motor, mathematically modeled using procedural sequence of equations. Induction motor speed control is employed by regulating the slip speed maintaining constant V/f. PI controller is implemented to ensure the motor speed at its reference speed. Closed loop scheme is tested for various reference speed and disturbances in dynamic load and speed. Comparative evaluation of transient and steady state performance characteristics, system efficiency and cost effectiveness is analyzed for closed loop MLI as well as VSI fed induction motor drive. MATLAB/SIMULINK setup, an effective tool for simulation is used for validating the results.

Comparative Analysis of Two Level VSI and Three Level Neutral Point Clamped Inverter for Torque Ripple Reduction in Induction Drive

This paper presents the comparative analysis of various level of multilevel inverter for induction motor torque ripple minimization. The neutralpoint clamped (NPC) inverter is used an adequate solution in AC drives application. The Conventional inverters compared to multilevel inverters have many limitations in high-voltage and high-power applications like poor power quality, high voltage stress, EMI/EMC issue etc. Also proposed the Space Vector neutral point clamped inverter for Torque ripple reduction in induction drive. The Simple Space vector control scheme is applied to neutral point clamped inverter by reference torque estimation. In this proposed topology offer an improved performance in the form of torque ripple reduction scheme. The Classical direct torque control of two-level VSI scheme is compared with proposed three-level NPC scheme. The main aim of this paper to provide a significant method and control scheme to obtained torque ripple reduction in induction motor Drive. The result shows the performance of neutral point clamped inverter using CB-PWM on induction drive. In this paper three levels VSI based Neutral Point Clamped (NPC) multilevel inverter fed induction motor drive is simulated, analyzed and compared with two levels VSI based NPC inverter drives. Torque of the motor is controlled by using space vector based direct torque control (DTC) method. The simulation results are carried out by using MATLAB/SIMULAINK environment.

SVPWM Based Two Level VSI for Micro Grids

SVPWM Based Two Level VSI for Micro Grids

EMBEDDED CONTROLLED MULTI LEVEL VOLTAGE SOURCE INVERTER BASED DISTRIBUTION STATICS SYNCHRONOUS COMPENSATOR

This study deals with the D-STATCOM used as a shunt connected compensator for the voltage support. The D-STATCOM has a faster response as compared with the conventional compensators such as the synchronous condenser and the SVC. The D-STATCOM can provide voltage support and improve power quality. The D-STATCOM supplies reactive power to the load to improve the voltage stability of the load busses. In this study two control strategies are performed using VSI fed STATCOM for reactive power compensation and power system bus voltage regulation. The fourteen bus system with and without D-STATCOM are modeled and simulated. VSI fed STATCOM is modeled and simulated. The compensators are tested with different loads. The above facts have been verified by using simulation in MATLAB/SIMULINK environment on a five level VSI fed STATCOM under variations of load. The simulated results have been validated through experimental results on a five level VSI fed STATCOM and the experimental results are compared with the simulated results.

Five Level VSI Based STATCOM In Fourteen Bus System

Five Level VSI Based STATCOM In Fourteen Bus System

Modified SVPWM Algorithm for Three Level VSI With Synchronized and Symmetrical Waveforms

The objective of the present work is to improve the output waveform of three level inverters used in high-power applications, where the switching frequency is very low. This is achieved by maintaining the synchronization, half-wave symmetry, quarter-wave symmetry, and three-phase symmetry in the pulsewidth modulation (PWM) waveforms. The principles of achieving synchronization and symmetries in terms of space vectors for three level inverters are presented. A novel synchronized space vector pulsewidth modulation (SVPWM) algorithms is proposed and verified experimentally. The experimental waveforms of the inverter output voltage and motor no load current for different operating conditions of the drive are presented. The performance measure in terms of the weighted total harmonic distortion (THD) of the line voltage is computed for the linear modulation region of the drive for the proposed algorithm and compared with that of synchronized SVPWM and synchronized sine-triangle pulsewidth modulation (SPWM) technique. The comparative results show that consideration of synchronization and symmetry results in improved THD. Another significant feature of the proposed algorithm is that the symmetry and synchronization leads to self-balancing of the direct current (dc) bus capacitor voltages over every one third cycle of the fundamental