Level Solder Joint Reliability Research Articles

Four-point bending cycling: The alternative for thermal cycling solder fatigue testing of electronic components

This paper deals with an alternative testing approach for quantifying the life time of board level solder joint reliability of components. This approach consists of applying a relative shear displacement between component and Printed Circuit Board (PCB) through cyclic board bending. During the cycling, the temperature is kept constant, preferably at elevated temperature in order to accelerate the creep deformation of the solder joint. This is done in a four-point bending setup which allows to apply an equal loading on all components lying between the inner bars. The scope of the paper is, firstly, to evaluate if the four point bending testing generates the same fatigue fracture as in thermal cycling; secondly, that the measured life times can be also predicted through finite element simulations; and thirdly if the technique can finally accelerate the cycling frequency to reduce the testing time.

PBGA Cost Reduction by Reducing Plated Au Thickness of Substrate Pads

In the past decade, we have witnessed the significant increase of gold price. Coupled with continuous price decrease of electronic products, the reduction of gold consumption has been explored in every possible area. This paper is related to reducing gold consumption on wire bonding pads of low density interconnect substrates. A layer of gold is plated on the substrate pads with typical minimum thickness of 0.5um to facilitate wire bonding process using gold wire. The objective of this study was to reduce gold thickness on the substrate pad to 0.3um minimum without compromising wire bond integrity. DOE considering different substrate sources wire bonded by different assembly suppliers were conducted. Wire bonding process optimization was followed by package level reliability stress testing, heat aging, and board level solder joint reliability testing was carried out for validation. The results showed plated gold thickness on the wire bond substrate pads can be reduced to a minimum of 0.3um without compromising package reliability performance. With the success of thinner gold on the substrate pads, we can use the same natural resources - gold to build more units, 'better for environment, if we consume less'

Modeling and Simulation of Electronic Packages Subjected to Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers, especially for handheld electronic products. These handheld electronic products are more prone to being dropped during their useful service life because of their small size and light weight. The electronic packages used in portable devices are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The dropping events not only induce mechanical failures in the housing of the device, but also lead to failure of PCB and components mounted on it. This work deals with: (a) Development of a simulation model of complete drop block with printed circuit board and plastic ball grid array (PBGA) assembly, which resembles actual drop test (free fall); (b) Development of an Input-G method for simulating the PCB dynamic responses; and (c) Comparison of results of free fall and Input-G methods. From the simulation results it was found that the mechanical shock causes multiple PCB bending and induce stresses in the solder balls of PBGA package. The solder balls at the outer rows of the PBGA package were subjected to maximum stress. Comparison of free fall drop and Input-G method results revealed that, the Input-G method uses less computer memory, takes less time to solve and it is simple to simulate the drop process.

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Wafer level packaging (WLP) has many advantages, such as ease of fabrication and reduced fabrication cost. However, solder joint reliability of traditional WLPs is the weakest point of the technology. In this paper, a 0.4 mm pitch Cu post type WLP has been developed for mobile computing application. The Cu post type WLP has 440 I/Os and 12 × 12 mm die size. The initial design WLP has been fabricated and subjected to a thermal cycling (TC) testing. The failure life of the original WLP under TC was 296 cycles. This paper also presents a nonlinear finite element analysis of the board level solder joint reliability and methods for enhancement of the WLP. A viscoplastic constitutive relation is adopted for the solder joints to account for its time and temperature dependence in TC. The fatigue life of the solder joint is estimated by the modified Coffin–Manson equation. The two coefficients in the modified Coffin–Manson equation are also determined. A series of parametric studies are performed by changing the passivation (PI) thickness, redistribution layer (RDL) thickness, polymer height (Cu post height accordingly varies), die thickness, PCB thickness, and PCB CTE. The results obtained from the modeling are useful to formulate design guidelines for board level reliability enhancement of the WLP.

Dynamic responses and solder joint reliability under board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. In this paper, the comprehensive dynamic responses of printed circuit boards (PCBs) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. Control and monitoring of dynamic responses are very important to ensure consistent test results and understand the mechanical behaviors, as they are closely related to the solder joint failure mechanism. The effects of test variables, such as drop height, number of PCB mounting screws, tightness of screws, and number of felt layer, are studied by comparing and analyzing the dynamic responses. A good repeatability of testing can only be achieved when careful attentions are paid on these factors. The relationships among drop height, peak acceleration, pulse duration, and impact energy are unique for a drop tester, and therefore, it should be characterized prior to the reliability tests. The studies also help to determine the requirements of new impact pulse quickly. The bending mode shapes and frequencies of PCB are extracted from dynamic strains and images token by high-speed camera. A real-time dynamic resistance monitoring method is developed to study the solder joint reliability. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint crack failure. Cyclic changes of dynamic resistance indicate that the solder joint crack opens and closes when PCB bends up and down.

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported

Advanced Numerical and Experimental Techniques for Analysis of Dynamic Responses and Solder Joint Reliability During Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e., crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints, dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when the PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross section and dye penetration tests

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.

Thermo-mechanical finite element analysis in a multichip build up substrate based package design

This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the second level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. First, the effect of the positioning of four silicon dice within the MCM package on the warpage of the package is studied. Second, the effect of package dimensions (the heat spreader thickness, the structural adhesive thickness and the substrate thickness) on the maximum residual stress as well as the warpage of the package is performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the Darveaux's approach. A series of parametric study is performed by changing the package dimensions. The results show that the largest die tends to experience highest stresses at its corner and has more influence on the warpage of the package than smaller dice. The results also show the most sensitivity factors that affect the package warpage and the second level solder joint reliability are the substrate thickness and the heat spreader thickness. The structural adhesive thickness has no major effect on the package warpage, the maximum von Mises stress of the package and the second level solder joint reliability.

Board Level Reliability Enhancement for A Double-bump Wafer Level Chip Scale Package

This paper presents a nonlinear finite element analysis on board level solder joint reliability enhancement of a double-bump wafer level chip scale package (CSP). A viscoplastic constitutive relation is adopted for the solders to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the modified Coffin-Manson equation, which has been verified by experimental results using one of the double-bump wafer level CSP packages as the test vehicle. A series of parametric studies were performed by changing the Sn/Ag inner bump size (UBM pad size and standoff height), the eutectic Sn/Pb external solder joint size (pad size and standoff height), pitch, die thickness, and the encapsulant thickness. The results obtained from the modeling are useful to form design guidelines for board level reliability enhancement of the wafer level CSP packages.

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.

DESIGN FOR BOARD LEVEL RELIABILITY OF A MINIATURIZED MEMS PACKAGE: STACKED DIE TQFN

International Journal of Computational Engineering ScienceVol. 04, No. 02, pp. 347-350 (2003) PackagingNo AccessDESIGN FOR BOARD LEVEL RELIABILITY OF A MINIATURIZED MEMS PACKAGE: STACKED DIE TQFNTONG Y. TEE, GIOVANNI FREZZA, MAYHUAN LIM, HUN S. NG, FEDERICO ZIGLIOLI, and ZHAOWEI ZHONGTONG Y. TEESTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , GIOVANNI FREZZASTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , MAYHUAN LIMSTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , HUN S. NGSTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , FEDERICO ZIGLIOLISTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , and ZHAOWEI ZHONGNanyang Technological University, School of MPE, 50 Nanyang Ave, Singapore 639798, Singapore Search for more papers by this author https://doi.org/10.1142/S1465876303001241Cited by:4 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractA new type of MEMS 3D package is introduced: stacked die Thick Quad Flat Non-lead (TQFN), for application as a multiple axis linear accelerometer. Both solder joint and die reliability during board level thermal cycling test are important concerns, as they affect the functionality and quality of the product. Design analyses are performed to study the effects of 12 key design variations in package dimensions and material properties, on solder joint reliability.Keywords:QFNStacked DieAccelerometerSolder Joint Reliability References R. Darveaux, Effect of Simulation Methodology on Solder Joint Crack Growth Correlation, Proc. 50th ECTC Conference, Las Vegas, NE (2000) 1048-1058 . Google Scholar T. Y. Tee, H. S. Ng, J. Diot, G. Frezza, R. Tiziani and G. Santospirito, Comprehensive Design Analysis of QFN and PowerQFN Packages for Enhanced Board Level Solder Joint Reliability, Proc. 52nd ECTC Conference, San Diego, CA (2002) 985-991 . Google Scholar T. Y. Tee, M. Lim, H. S. Ng, X. Baraton, D. Kaire and Z. W. Zhong, Design Analysis of Solder Joint Reliability for Stacked Die Mixed Flip-Chip and Wirebond BGA, Proc. 4th EPTC Conference, Singapore (2002) 391-397 . Google ScholarW. W. Lee, L. T. Nguyen and G. S. Selvaduray, Microelectronics Reliability 40, 231 (2000). Crossref, Google Scholar FiguresReferencesRelatedDetailsCited By 4Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packagesTong Yan Tee and Zhaowei Zhong1 Dec 2004 | Microelectronics Reliability, Vol. 44, No. 12Absolute and relative fatigue life prediction methodology for virtual qualification and design enhancement of lead-free BGA Hun Shen Ng, Tong Yan Tee, Kim Yong Goh, Jing-en Luan and T. Reinikainen et al.Design analysis of touch chip for enhanced package and board level reliability Tong Yan Tee, Hun Shen Ng, H. Siegel, R. Bond and Zhaowei Zhong4-Dimensional Design Analysis and Optimization of System-in-Package Tong Yan Tee, Hun Shen Ng, Jing-en Luan, Xueren Zhang and Kim Yong Goh et al. Recommended Vol. 04, No. 02 Metrics History KeywordsQFNStacked DieAccelerometerSolder Joint ReliabilityPDF download

Assessment of board level solder joint reliability for PBGA assemblies with lead‐free solders

Evaluates the board level reliability of plastic ball grid array (PBGA) assemblies under thermal and mechanical loading, with the objective of characterizing the reliability of lead‐free solder joints for various assembly conditions. A five‐leg experiment was designed which included various combinations of solder materials and peak reflow temperatures. It was found that the lead‐free solder joints have a much longer thermal fatigue life than the 63Sn–37Pb solder. The 63Sn–37Pb solder joints seem to perform slightly better than the lead‐free solder under mechanical loading.

Computational parametric analyzes on the solder joint reliability of bottom leaded plastic (BLP) package

The bottom-leaded plastic (BLP) package is a lead-on-chip type of chip scale package (CSP) developed mainly for memory devices. Because the BLP package is one of the smallest plastic packages available, solder joint reliability becomes a critical issue. In this study, a 28-pin BLP package is modeled to investigate the effects of molding compound and leadframe material properties, the thickness of printed circuit board (PCB), the shape of solder joint and the solder pad size on the board level solder joint reliability. A viscoplastic constitutive relation is adopted for the modeling of solder in order to account for its time and temperature dependence on thermal cycling. A three-dimensional nonlinear finite element analysis based on the above constitutive relation is conducted to model the response of a BLP assembly subjected to thermal cycling. The fatigue life of the solder joint is estimated by the modified Coffin-Manson equation. The two coefficients in the modified Coffin-Manson equation are also determined. Parametric studies are performed to investigate the dependence of solder joint fatigue life on various design factors.

Interfacial reaction and solder joint reliability of Pb-free solders in lead frame chip scale packages (LF-CSP)

Chip scale packages (CSP) have essential solder joint quality problems, and a board level reliability is a key issue in design and development of the CSP type packages. There has been an effort to eliminate Pb from solder due to its toxicology. To evaluate the various solder balls in CSP package applications, Pb-free Sn-Ag-X (X=In, Cu, Bi) and Sn-9Zn-1Bi-5In solder balls were characterized by melting behavior, phases, interfacial reaction, and solder joint reliability. For studying joint strength between solders and under bump metallurgy (UBM) systems, various UBMs were prepared by electroplating and electroless plating. After T/C (temperature cycle) test, Sn3.5Ag8.5In solder was partially corroded and its shape was distorted. This phenomenon was observed in a Sn3Ag10In 1Cu solder system, too. Their fractured surface, microstructure of solder joint interface, and of bulk solder ball were examined and analyzed by optical microscopy, SEM and EDX. To simulate the real surface mounting condition and evaluate the solder joint reliability on board level, Daisy chain test samples using LF-CSP packages were prepared with various Pb-free solders, then a temperature cycle test (−65∼ 150°C) was performed. All tested Pb-free solders showed better board level solder joint reliability than Sn-36Pb-2Ag. Sn-3.5Ag-0.7Cu and Sn-9Zn-1Bi-5In solders showed 35%, 100% superior solder joint reliability than Sn-36Pb-2Ag solder ball, respectively.