Level-shifted Pulse Width Modulation Research Articles

An FPGA-based balancing of capacitor voltage for multi-level inverter

ABSTRACT This paper introduces a novel cascaded multilevel inverter circuit configuration aimed at generating a five-level load voltage using a single DC source and a capacitor. In this inverter configuration, an additional switch is added to the charging circuit which helps to charge the capacitor from the DC source. Additionally, an inductor is incorporated to mitigate the substantial charging current during capacitor charging operation. A level-shifted pulse width modulation (LS-PWM) technique is implemented to generate gate pulses for both inverter and charging switches. The capacitor gets charged when an extra switch is enabled and discharged when it is connected to a load. Analysis of charging and discharging of capacitor is described thoroughly in this paper. Each operational mode of the inverter is thoroughly analysed. Furthermore, the proposed five-level inverter setup is designed, and its control logic is implemented using FPGA platform. Subsequently, simulation and experimental investigations are conducted under varied loads and different modulation indices to evaluate the efficacy of the proposed inverter configuration and the respective results are presented.

Harmonizing power systems with a 13-level modified Packed U-Cells multi-level inverter: Design and implementation

Traditional multilevel inverter designs often face complexity challenges, prompting the need for a simplified solution. This study introduces and evaluates the performance of a Modified Packed U-Cells (MPUC) inverter in the realm of multilevel inverter technology. The study addresses challenges associated with conventional multilevel inverters and proposes the MPUC inverter as a solution to simplify the design complexity. The MPUC inverter, utilizing three DC sources and eight switches, presents a groundbreaking thirteen-level output waveform. The primary focus lies in assessing the inverter's performance in terms of Total Harmonic Distortion (THD) and output voltage. Utilizing MATLAB/Simulink, the inverter's performance is evaluated with and without Pulse Width Modulation (PWM) strategies. The results reveal a notable reduction in THD, from 26.25% to 9.91% post-filtering when PWM is not employed. Various multi-carrier Level-Shifted PWM strategies, including PDPWM, PODPWM, APODPWM, and COPWM, are explored to enhance output waveform smoothness and efficiency. Unequal Carrier strategies, specifically UEAPDPWM and UEAPODPWM, emerge as superior in THD management at different frequency ranges. The study further incorporates real-time hardware implementation of the proposed 13-level MPUC topology, highlighting the success of the UEAPD-PWM strategy in improving waveform quality. The research aims to establish a multilevel inverter design protocol meeting international standards and emphasizes the pivotal role of PWM techniques in enhancing waveform quality. This comprehensive evaluation contributes to advancing the field of multilevel inverter technology and sets a benchmark for future research in this domain.

Detection and Localization of Open Switch Faults for Level-Shifted PWM Cascaded H-Bridge Inverter

Detection and Localization of Open Switch Faults for Level-Shifted PWM Cascaded H-Bridge Inverter

A 17-level quadruple boost switched-capacitor inverter with reduced devices and limited charge current

In this paper, a quadruple boost switched-capacitor multi-level inverter is proposed. The proposed structure utilizes a DC source, 11 switches, and a diode to achieve 17-level output voltage levels. This structure consists of three capacitors with the ability for self-balancing voltages. The capacitors achieve automatic voltage balancing through a series/parallel connection with the input voltage source. To control the switching pulses of the switches, level-shifted pulse width modulation (LS-PWM) strategy has been employed. A comparative evaluation has been performed between the proposed structure and structures presented in recent articles, considering various parameters such as voltage gain, number of DC sources, number of semiconductor devices, maximum blocking voltage (MBV), and total standing voltage (TSV). Considering this comparison, the lower number of semiconductor devices for generating a 17-level output with suitable voltage gain, and especially the cost-effectiveness of the structure, are the main advantages of the proposed configuration. In addition, a soft charging method has been employed to limit the inrush current of capacitors. Moreover, the power losses of the proposed structure have been investigated, indicating its acceptable efficiency. Finally, for the analysis and validation of the proposed structure's performance, an experimental prototype has been implemented and evaluated under various conditions. The results indicate satisfactory performance of the proposed structure under various stable and dynamic operating conditions.

Nine level switched capacitor inverter with level shifted pulse width modulation approach

This article proposes a nine-level switched capacitor inverter (NLSCI) with a minimum number of switches. In recent years, switching capacitor (SC) multilevel inverters (MLIs) have become one of the most common inverter topologies. These proposed nine level switched capacitor inverter (NLSCI) do not deserve any external control unit for capacitor control. Since, the charging and discharging of the capacitors are controlled by the on and off states of switches. Furthermore, by employing fewer switches and DC voltage sources, the suggested design produces a greater amount of resultant voltage. Additionally, pulse width modulation (PWM) is recommended as a method to enhance output quality and power level quality. The switched-capacitor two-output multilevel inverter (SCMLI) structure's viability and effectiveness have been demonstrated using MATLAB simulation.

A Novel Hybrid PWM Technique for Asymmetric Inverter

Multi-Level Inverters (MLIs) are achieving broad popularity owing to the rapid development of power semiconductor devices. The capability of MLIs became recognized as a significant aspect of a system heavily reliant on Pulse Width Modulation(PWM) strategy. The conventional high frequency PWM techniques suffer from significant Total Harmonic Distortion (THD) along with power loss difficulties. This work recommends a hybrid PWM technique for lowering the THD and power loss of VSI adding the benefits of level-shift PWM and Phase-shift PWM. A novel form of carrier signals is employed in the proposed hybrid PWM technique. In contrast to existing PWM techniques, the proposed hybrid PWM technique minimizes switching and conduction power losses. In this work, the proposed PWM scheme is employed for asymmetric multilevel inverter. The proposed configuration is also examined using PLECS software to estimate losses and efficiency. The simulation work is done in the MATLAB/Simulink environment and the OPAL-RT(OP4510) test platform is employed to evaluate topology performance.

New modified carrier-based level-shifted PWM control for NPC rectifiers considered for implementation in EV fast chargers

New modified carrier-based level-shifted PWM control for NPC rectifiers considered for implementation in EV fast chargers

An Analysis and Optimization of the Battery Capacity Difference Tolerance of the Modular Multi-Level Half-Bridge Energy Storage Converter

As a power converter of battery energy storage, the multi-level converter and its battery balancing control have received much attention from scholars. This paper focuses on the modular multi-level half-bridge energy storage converter (MMH-ESC), including its topology, working principle, and pulse width modulation (PWM) methods. Under the battery balancing control strategy based on level-shifted carrier PWM (LS-PWM), formulas are derived and calculations are performed to get the charge or discharge of each submodule (SM), thereby obtaining the tolerance for capacity differences among these batteries. A range of battery capacity values that can maintain a balanced state is provided to enhance flexibility in battery configuration and utilization, avoiding the limitation of all batteries to the same capacity. Finally, a new bridge arm modulation wave allocation method is proposed. This method significantly expands the range of SM battery capacity selection and provides a high-tolerance modulation method for the converter under extreme or even fault conditions.

Switched Capacitor Based Cascaded Half-Bridge Multilevel Inverter with Voltage Boosting Feature

Abstract: In many applications, cascading multilevel inverter (CMI) topologies are common. However, the biggest disadvantage of CMI is the need for many separate switches and DC sources. As a result, the CMI topology becomes more expensive, more complex, and larger, and its performance suffers. In the proposed SC-CHMI, only one DC source is used and the other DC sources are replaced by switched capacitor cells. Thanks to the self-balancing function, the capacitor charging process occurs naturally without the need for any auxiliary equipment. In the proposed SC-CHMI, the inrush current of the capacitor is attenuated using a load inductor or a front-end boost converter. To improve the performance of multi-level inverters, several types of techniques can be tested with existing multi-level inverters. Due to the modulation algorithm, modulation frequency, voltage drop on the switches and bus voltage modulation, the output voltage of the inverter has overall harmonic distortion, leading to overheating of the device and shortening the life of the device bag. In the proposed SC-CHMI, a level-shifted pulse width modulation technique is proposed to improve the output voltage quality and reduce the total harmonic distortion. This new control scheme is applicable to nine-level, eleven-level and fifteen-level SC-CHMI. The proposed topology can be used as a general-purpose inverter in renewable energy systems, due to its voltage gain characteristics, minimal number of switches, and single DC source. The effectiveness of the proposed inverter topology is confirmed by simulation results.

Switched capacitor based 7-level and 9-level multilevel inverters with single DC source and reduced voltage stress

This paper proposes two different switched capacitor based Multilevel Inverter topologies having single dc voltage source. One of the proposed MLIs is a seven-level structure whereas the other circuit successfully generates a nine-level output voltage. The special features of the seven-level topology consist of reduced number of circuit elements, lower voltage stress on switches, and boosted output voltage. The nine-level MLI having unity gain also possess the reduced switch count along with lower value of switch voltage stress. Fundamental frequency based Nearest Level Control modulation and Level-Shifted Pulse Width Modulation have been used for generating the required voltage levels. Successful implementation of the proposed MLI circuits has been done with the help of a laboratory prototype and its results are presented and explained in the paper to show its practical suitability. Other type of analysis include loss analysis which has been done in PLECS software. From this analysis, the efficiency has been estimated. A comparative analysis of both the proposed structures has been carried out with some other similar topologies on different performance parameters. From the analysis and comparison, it is evident that the proposed MLIs are better than some of the existing topologies and can be used for industrial applications.

Compact three‐phase multilevel inverter with boosting capability for low‐power three‐phase induction motor drive

SummaryThis paper proposes a step‐up three‐phase multilevel inverter based on switched capacitor (SC) cells. The prominent features of this inverter are the reduction of the number of components (such as switches, capacitors, and sources) and the ability to boost the voltage. Also, the self‐voltage balancing of the capacitors of this inverter is one of the other features of this inverter. The level‐shifted pulse width modulation (LS‐PWM) method has been used for switching, making the output currents' total harmonic distortion (THD) low. The article has presented the experimental results of this inverter with a three‐phase induction motor with a power of 1.1 kW as a load.

Efficiency of Series APF based on Nine-level NPC Inverter Compared to Seven-level Configuration

This article presents the performance comparison of Series Active Power Filter (Series APF) based on seven and nine multi-level Neutral Point Clamped (NPC) inverters using the same control scheme. The Series APF is one of the most efficient and effective modern custom power devices used in power distribution networks to compensate voltage harmonic and all voltage disturbances. The conventional configuration based on voltage source inverter (VSI) operated at very high switching frequency presents several drawbacks and limited for low power applications. To overcome these problems and improve the output voltage different multi-level are used in various power application in particular Flying Capacitor (FC), Cascade H-Bridge (CHB) and multi-level (NPC) inverters. In this study seven and nine-level (NPC) inverters are proposed for active power filtering system; these inverters present diverse advantages include the capability to reduce the harmonic content, decrease the voltage or current ratings of the semiconductors and mainly they can work at low switching frequency. To generate switching pulses Multi-Carrier Level-Shifted Pulse Width Modulation (MC-LSPWM) control technique is adopted with modified P-Q control strategies. To verify the accuracy and the performance of the proposed Series APF models, simulation is performed using MATLAB-Simulink platform and SimPowerSystem Toolbox. The obtained results show the superiority of series APF based on nine-level in term of THDv reduction compared to the systems with seven-level inverter topology.

Comparative performance of modular with cascaded H-bridge three level inverters

<span lang="EN-US">The conventional two-level inverter becomes no longer has the ability to cope with the high-power requirement, so this paper discusses two very common topologies of multilevel inverter like modular multi-level converter (MMC) and cascaded H-bridge (CHB) multi-level inverter for induction motor drive applications. This work attempts to investigate the comparison between MMC and CHB. The comparison is done in aspects of the configuration, concept of operation, advantages and disadvantages, the comparison is also consider output voltage (line to line) waveform, total harmonic distortion (THD) of the output line voltage waveform and the current drawn by both inverters. The performance of the inverters under carrier-based pulse width modulation (PWM) technique and mainly in-phase disposition (IPD), level shifted pulse width modulation is viewed. The paper discusses the comparison between the two multilevel inverters (MLIs) with motor drive applications especially induction motor. The operation of the motor is studied under certain value of load torque. The simulation results for the induction motor with the two inverters (modular multi-level and Cascaded H-bride) for three numbers of levels using MATLAB/Simulink are provided). The obtained results are encouraging and promising especially in the improvement of the THD% results.</span>

Self-Balanced Nine-Level Flying Capacitor Inverter With Double-Period Level-Shifted Control

Voltage imbalance and peak charging current often occurs in capacitor-containing inverters. To solve this problem, a nine-level flying capacitor inverter and a double-period level-shifted pulse-width modulation (DPLS-PWM) strategy is proposed. The proposed topology has the advantage of reduced capacitor count and low total standing voltage (TSV). Owing to the special redundant states of proposed inverter, a DPLS-PWM is introduced. By applying DPLS-PWM strategy, the two capacitors in the proposed inverter can be balanced naturally. Meanwhile, unlike most switched-capacitor (SC) inverters whose self-balance scheme often generate large inrush current, the current stress of the proposed balance scheme is low. The working modes of proposed inverter and the principles of DPLS-PWM is analyzed in detail. And comparisons are made to highlight the merits of the topology and modulation method. Simulation and experimental results have verified the feasibility of the proposed topology and self-balance modulation. The experimental efficiency of this inverter can reach over 98%.

Performance improvements of power converters for high power induction motor drive

This paper deals with a reliable transformer configuration with simple wiring and less number windings for twenty-four pulse AC-DC converter, which is used in medium voltage drive system so that it can adverse the effects produced by harmonics currents fed into the grid by converters that do not affect other consumers connected to the same electrical grid. Apart from this, a five-level symmetrical multilevel inverter configuration is used by cascading four two-level voltage source inverters. It is designed with less quantity of components counts like; power switches, diodes and electrolytic capacitors. Because power quality impacts the suitability of electrical power for consumer electronics, an attempt is made in this work to improve power quality through the connecting high-pulse converter at the grid end instead of 12-pulse and modified level-shifted pulse width modulation for a multi-level inverter at the drive end. Performance of the described topology is verified in the laboratory using a drive-through MATLAB/Simulink environment and a prototype at a reduced scale. The feasibility and effectiveness of the proposed topology are demonstrated by a comprehensive comparison with recently reported schemes. Promising results validate this new concept.

Symmetrical Cross-Connected T-Type Multilevel Inverter With Reduce Device Count

This paper presents a symmetrical, cross-connected T-type (CT-type) multilevel inverter (MLI) configuration with reduced device count (RDC). It comprises eight power switches, two DC sources, and four capacitors with self-voltage balancing. The generalized topology is formed by two CT-type basic modules connected by two power switches. These topologies operate using DC sources and capacitors having the same or different voltage levels, which can be extended by cascading the modules to attain a higher voltage level suitable for high-power applications. Therefore, the proposed CT-Type MLI is a good choice for renewable energy applications that require a lower input voltage source magnitude to attain high voltage levels. This paper uses the Matlab/Simulink platform to simulate the proposed CT-type topology using the level-shifted pulse width modulation (LS-PWM) technique. Further, a laboratory prototype is developed to test and validate the feasibility and effectiveness of the proposed MLI. Finally, a comparative analysis of the number of DC sources, capacitors, power switches, drivers, and total standing voltage (TSV) is presented against similar recent topologies.

Self-aligned hybrid carrier-based PWM for modular multilevel converters

The self-aligned hybrid carrier-based pulse-width modulation (PWM) for modular multilevel converters (MMC) based on decentralized control is proposed in this paper. It is based on parallel cells in a submodule (SM) using self-aligned hybrid carrier-based PWM, which combines the concept of level-shifted carrier-based PWM (LSC-PWM) and phase-shifted carrier-based PWM (PSC-PWM) methods. By implementing a decentralized control system digitally, hybrid carriers align themselves. Each SM interacts with the other SMs and each parallel cell in an SM communicates with the other cells to generate hybrid carriers. The proposed control strategy makes advantage of the redundancy idea by adding or removing a cell in the case of cell malfunction and system reconfiguration. A current balancing method is incorporated into the decentralized control system to ensure current balance among parallel cells in an SM. The simulation results illustrate the effectiveness of the presented control method in piecewise linear electrical circuit simulation (PLECS) software.

Capacitor-Voltage-Balancing Control for Isolated Medium-Voltage AC-DC Modular Matrix Converter

This paper presents a capacitor-voltage-balancing control scheme for an isolated medium-voltage AC-DC converter using level-shifted PWM control of a modular matrix converter (MMxC). The proposed isolated AC-DC converter is composed of the primary MMxC with level-shifted PWM control, high-frequency transformer, and secondary H-bridge circuits. The high-frequency transformer of the proposed circuit can be downsized because the level-shifted PWM control scheme makes the rated frequency of the high-frequency transformer equal to the switching-frequency. The proposed capacitor-voltage-balancing control can compensate for the capacitor voltage imbalance of the MMxC using the positive-sequence and negative-sequence circulating-currents with a power supply frequency and high-frequency voltage. In the proposed control system, the three feedback control systems with DC control variables can be developed to compensate for the capacitor voltage imbalance. The effectiveness of the proposed capacitor-voltage-balancing control scheme and the control systems is verified by experiments using a 200V, 5-kW laboratory prototype.

High Reliable Medium Voltage Drive With Reduced Component Count of Converters

The rapid development of technology, particularly in the fields of medium-voltage drive applications, has led to the widespread and use of AC to DC multi-pulse and DC to AC multilevel converters. In recent years, multi-winding transformers (MWTs)-based multi-pulse converters have received significant attention, owing to the growing need to utilize the energy as per power quality standards with high reliability in medium voltage drive systems. The main issues of multi-pulse converters are the large complexity of winding connections, which directly degrades the reliability of the system and increases the requirement for conductor material. To address these issues of grid-end converters, this paper suggests a less complex structure of a multi-winding transformer (MWT) for a thirty-six pulse AC-DC converter, which demands the least conductor material for windings. Moreover, the reduction in the number of components of the multi-level inverters has a noticeable role in saving size, cost, and reliability improvement. To address these features in the drive system, a five-level hybrid symmetric cascaded H-bridge multilevel inverter (HSCHB-MLI) is presented, which performs a high-quality power conversion at the motor terminals of the drive system. Hence, the main concerns of this drive system are the reduction in the component count, weight, and losses of the system with excellent harmonics performance. The operational aspects of the topology such as circuit structure, design, and indirect field-oriented control (IFOC), and modulation technique (parabolic carrier wave-based level shifted pulse width modulation) are elaborated in detail. A detailed comparative assessment is performed with other multi-winding transformers and multi-level inverter structures to demonstrate the merits of the presented multi-winding transformer and multilevel inverter structures, respectively. Finlay, through Simulink modeling and hardware testing setup, the viability of the proposed architecture is verified.

A novel PWM technique for reduced switch count multilevel inverter in renewable power applications

This paper described a novel pulse width modulation (PWM) technique in reduced switch count multilevel inverter (MLI) for renewable power applications. Therefore, the proposed technique finds a better solution in the multilevel inverters used for improving power quality, efficiency and reduction of switching and conduction losses. It produces a smoother sinusoidal output waveform with reduced total harmonic distortion (THD) using different modulation technique. The novel PWM technique consists of nearest level control (NLC) and level shift pulse width modulation (LSPWM). Normally semiconducting devices are added for increasing number of levels. It affects the power quality and efficiency due to losses. In this work, MLI topology with reduced number of switches count for NLC and LSPWM is presented. The single-phase and three-phase inverter configuration is used in proposed mythology. Detailed simulation results for 7-level inverter of single and three-phase inverters are presented in this paper. It is observed that NLC method is better efficiency and reduced THD than LSPWM for better utilization in renewable power applications.