Level-shifted Pulse Width Modulation Research Articles

Research on a Thirteen-Level Switched Capacitor Inverter with Low Switching Loss

This paper presents a 13-level switched capacitor inverter with a novel modulation method designed to minimize the number of switches and significantly reduce switching losses. The inverter stands out for its simplicity, requiring only ten semiconductor switches to generate 13 levels. A key feature is the inherent self-voltage balancing of the capacitors, which eliminates the need for additional control mechanisms. The inverter’s unique architecture, comprising high-voltage and low-voltage modules, enables modulation using a hybrid PWM approach that combines step waveform modulation with level-shifted PWM (LS-PWM). This innovative technique dramatically lowers the switching frequency of the high-voltage module’s switches, independent of the carrier frequency, thereby limiting the number of switches in high-frequency operation and achieving substantial reductions in switching losses. This paper provides a detailed analysis of the inverter’s operating modes, voltage-balancing mechanisms, and parameter calculations. The advantages of the topology presented in this paper are demonstrated by comparison. Finally, the simulation and experimental results confirm the practicality and effectiveness of the proposed inverter and its modulation strategy.

Comprehensive Analysis of Faults and Diagnosis Techniques in Cascaded Multi-Level Inverters

Reliability is a crucial factor to consider for multi-level inverters (MLIs) used in industrial applications. With the increasing number of power semiconductor devices, the potential for defects to significantly degrade the overall system is heightened. A highly effective fault-detection technique is required to minimize the impact of faults. This paper provides a comprehensive overview of the fundamental principles of multi-level inverters and the various sorts of faults that can occur in multi-level inverters. This study provides a comprehensive analysis of five-level cascaded H-bridge multilevel inverters (MLIs) under both normal and defective conditions. The paper outlines a fault-detection method that utilizes total harmonic distortion and a normalized output voltage factor. In addition, the paper discusses a fault-isolation strategy that relies on reducing amplitude modulation. This method leads to the development of a fault-tolerant inverter. The utilization of level-shifted pulse-width modulation (LSPWM) technology is employed for the purpose of switching operations. LSPWM is the most appropriate technique for MLIs that require a low amount of computational resources. The fault-diagnosis approach given is suitable for MLI-based drives, grid-connected operations, and other applications. This paper presents a comprehensive examination of the 5L-CMLI (5-Level Cascaded Multi-Level Inverter) under various fault scenarios in CMLI. Subsequently, various fault diagnosis approaches will be examined, including their advantages and disadvantages. The paper discusses several defects that can occur in the Insulated Gate Bipolar Transistor (IGBT) of a Current Mode Logic Inverter (CMLI), and also presents a design for a reliable fault diagnosis system. Furthermore, this analysis examines several fault detection strategies in CMLI, categorized according to open-loop and closed-loop dynamic systems fault classifications.

Analysis of Cascaded H Bridge Multilevel Inverter for Three-Phase Induction Motor Drive

The last ten years have seen a rise in the usage of multilayer inverters. Because they can produce waveforms with a greater harmonic spectrum and reliable output. Several high voltages and high-power applications are suitable for these new inverters. A multilayer converter not only produce high power ratings, but it also saves time and money and enhances the system performance in terms of harmonics, dv/dt strains, and pressures on the motor bearings. Owing to its flexibility and modularity, the possible topology for a power application is the cascaded H-bridge multilevel inverter (CMI) with separated DC sources. This study investigates a cascade H bridge multilevel inverter, such as a Three, Five, Seven, Nine and Eleven level inverter in order to drive a three phase AC induction motor. A Level shifted Pulse Width Modulation (LSPWM) technique was applied for the CHBMLI. Specific emphasis is given to aspects like modulation and total harmonic distortion that are preferable or necessary for multi-level converters. For both intellectual and scientific considerations, investigating sine triangle carrier pulse width modulation is deemed to be the most auspicious approach. Analysis of the many performance parameters, including load torque, motor speed, and efficiency, an extensive survey is conducted. MATLAB / Simulink is built into the entire system, and simulation results are developed. The purpose of this research is to demonstrate the performance of 9-level and 11-level fed induction motor driving results for Electric Vehicle applications. CHBMLI fed motor drive is better suitable for Induction Motor Drives.

A new single-source, single-phase, 9-L 4-B switched capacitor-based multilevel inverter

ABSTRACT All types of non-conventional energy sources (NCES) produce low voltage, but offer it to be converted into usable and essential form. Switched capacitor multilevel inverter (SC-MLIs) has played a vital role in extracting power from NCES to fulfill the requirements of today’s need. Researchers have shown a great interest in extracting this power which comes from solar PV, wind, fuel cells and other miniature sources which is often not significant at all. This research offers a topology that is very simple and easy to implement. The authors also demonstrate a novel SC-MLI with a single ground and four voltage boosting capabilities. This paper analyzes and reviews the suggested inverter can create nine levels along with four times the voltage from a single dc source. Three self-balanced switched capacitors in association with a pair of five switches and single diode are used to offer quadruple boosting. A level-shifted pulse width modulation technique helps to generate the output voltage. The execution of the SC-MLI and the capacitor architecture for the suggested topology are fully investigated. The availability of common neutral is advantageous in reducing leakage current, especially in green energy utilization. In the context of voltage gain, the number of components employed, and the presence of common neutral, the designed inverter is contrasted to several other previously revealed inverters.

Experimental Investigation of Modified Level Shift PWM with Capacitor Voltage Balancing on Single Phase Modular Multilevel Converter

Modular Multilevel Converters (MMCs) are a prominent voltage source converter topology that is rapidly gaining popularity in medium/high power/voltage applications, including high-voltage DC transmission systems and electric vehicle systems. However, MMC has the critical issue of unbalanced submodule capacitor voltages and circulating current. The MMC distributes DC-link energy evenly among its submodule capacitors, rather than storing it in a large capacitor like conventional voltage source converters. In MMC, the submodule floating capacitors interface the DC input voltage and AC output voltage. Therefore, capacitor voltages must be balanced. The existing capacitor voltage control struggles to handle many gate pulses at medium and high voltages. An effective control scheme is needed to solve the issues mentioned earlier. This paper presents a performance analysis of a 1-Φ MMC using a modified level shift PWM technique based on Universal Control Modulation Scheme (UCMS) and a sorting-based capacitor voltage balancing algorithm. MATLAB/Simulink software implements the proposed control method for a 1-Φ , seven-level MMC. The outcomes of the simulation demonstration reveal that phase disposition PWM offers less harmonic distortion of output phase voltage than the other level shift PWM techniques, such as phase disposition PWM and alternate phase disposition PWM. The simulation results also demonstrate the effective use of the sorting-based capacitor balancing algorithm to regulate the voltages of the submodule capacitors. Finally, the real-time GUI tool validates the simulation results using an experimental prototype of 1-Φ MMC with the dSPACE MicroLabBox 1202.

3-level inverter based compensator for power quality enhancement using proposed Trianguzoidal PWM technique

In today’s scenario, the integration of a grid-connected load system with a hybrid energy system (HES) is encouraged to improve the reliability of the system. With the stunning rise in nonlinear loads in HES over the last two decades, the power quality (PQ) of the system has emerged as a paramount concern in contemporary times. The power quality problems include the injection of harmonics in the source current, low input power factor, poor voltage regulation, the burden of reactive power, etc. So, to mitigate these power quality problems in a single-phase distribution system, a 3-level Cascade H-bridge (CHB) inverter-based shunt active power filter (SAPF) is employed alongside a proposed Trianguzoidal pulse width modulation (TRZ PWM) strategy. The single-phase distribution system with SAPF is simulated in fixed and dynamic load conditions to check the system’s efficacy. The proposed PWM techniques for SAPF are compared with conventional PWM techniques, i.e., level shift, phase shift, and hybrid PWM techniques. Results indicate satisfactory performance of the proposed PWM techniques, exhibiting low harmonic distortion in source current, well within IEEE 519 limits, and high active filtering efficiency (AFE) compared to conventional PWM methods. Furthermore, this paper provides detailed comparisons of conventional and proposed PWM techniques in the context of active & reactive power supplied or delivered by load, source, and compensator, input power factor, harmonics in source or grid current, AFE, and individual harmonic components concerning fundamental component of source current.

An FPGA-based balancing of capacitor voltage for multi-level inverter

ABSTRACT This paper introduces a novel cascaded multilevel inverter circuit configuration aimed at generating a five-level load voltage using a single DC source and a capacitor. In this inverter configuration, an additional switch is added to the charging circuit which helps to charge the capacitor from the DC source. Additionally, an inductor is incorporated to mitigate the substantial charging current during capacitor charging operation. A level-shifted pulse width modulation (LS-PWM) technique is implemented to generate gate pulses for both inverter and charging switches. The capacitor gets charged when an extra switch is enabled and discharged when it is connected to a load. Analysis of charging and discharging of capacitor is described thoroughly in this paper. Each operational mode of the inverter is thoroughly analysed. Furthermore, the proposed five-level inverter setup is designed, and its control logic is implemented using FPGA platform. Subsequently, simulation and experimental investigations are conducted under varied loads and different modulation indices to evaluate the efficacy of the proposed inverter configuration and the respective results are presented.

Harmonizing power systems with a 13-level modified Packed U-Cells multi-level inverter: Design and implementation

Traditional multilevel inverter designs often face complexity challenges, prompting the need for a simplified solution. This study introduces and evaluates the performance of a Modified Packed U-Cells (MPUC) inverter in the realm of multilevel inverter technology. The study addresses challenges associated with conventional multilevel inverters and proposes the MPUC inverter as a solution to simplify the design complexity. The MPUC inverter, utilizing three DC sources and eight switches, presents a groundbreaking thirteen-level output waveform. The primary focus lies in assessing the inverter's performance in terms of Total Harmonic Distortion (THD) and output voltage. Utilizing MATLAB/Simulink, the inverter's performance is evaluated with and without Pulse Width Modulation (PWM) strategies. The results reveal a notable reduction in THD, from 26.25% to 9.91% post-filtering when PWM is not employed. Various multi-carrier Level-Shifted PWM strategies, including PDPWM, PODPWM, APODPWM, and COPWM, are explored to enhance output waveform smoothness and efficiency. Unequal Carrier strategies, specifically UEAPDPWM and UEAPODPWM, emerge as superior in THD management at different frequency ranges. The study further incorporates real-time hardware implementation of the proposed 13-level MPUC topology, highlighting the success of the UEAPD-PWM strategy in improving waveform quality. The research aims to establish a multilevel inverter design protocol meeting international standards and emphasizes the pivotal role of PWM techniques in enhancing waveform quality. This comprehensive evaluation contributes to advancing the field of multilevel inverter technology and sets a benchmark for future research in this domain.

Detection and Localization of Open Switch Faults for Level-Shifted PWM Cascaded H-Bridge Inverter

Detection and Localization of Open Switch Faults for Level-Shifted PWM Cascaded H-Bridge Inverter

A 17-level quadruple boost switched-capacitor inverter with reduced devices and limited charge current

In this paper, a quadruple boost switched-capacitor multi-level inverter is proposed. The proposed structure utilizes a DC source, 11 switches, and a diode to achieve 17-level output voltage levels. This structure consists of three capacitors with the ability for self-balancing voltages. The capacitors achieve automatic voltage balancing through a series/parallel connection with the input voltage source. To control the switching pulses of the switches, level-shifted pulse width modulation (LS-PWM) strategy has been employed. A comparative evaluation has been performed between the proposed structure and structures presented in recent articles, considering various parameters such as voltage gain, number of DC sources, number of semiconductor devices, maximum blocking voltage (MBV), and total standing voltage (TSV). Considering this comparison, the lower number of semiconductor devices for generating a 17-level output with suitable voltage gain, and especially the cost-effectiveness of the structure, are the main advantages of the proposed configuration. In addition, a soft charging method has been employed to limit the inrush current of capacitors. Moreover, the power losses of the proposed structure have been investigated, indicating its acceptable efficiency. Finally, for the analysis and validation of the proposed structure's performance, an experimental prototype has been implemented and evaluated under various conditions. The results indicate satisfactory performance of the proposed structure under various stable and dynamic operating conditions.

Nine level switched capacitor inverter with level shifted pulse width modulation approach

This article proposes a nine-level switched capacitor inverter (NLSCI) with a minimum number of switches. In recent years, switching capacitor (SC) multilevel inverters (MLIs) have become one of the most common inverter topologies. These proposed nine level switched capacitor inverter (NLSCI) do not deserve any external control unit for capacitor control. Since, the charging and discharging of the capacitors are controlled by the on and off states of switches. Furthermore, by employing fewer switches and DC voltage sources, the suggested design produces a greater amount of resultant voltage. Additionally, pulse width modulation (PWM) is recommended as a method to enhance output quality and power level quality. The switched-capacitor two-output multilevel inverter (SCMLI) structure's viability and effectiveness have been demonstrated using MATLAB simulation.

A Novel Hybrid PWM Technique for Asymmetric Inverter

Multi-Level Inverters (MLIs) are achieving broad popularity owing to the rapid development of power semiconductor devices. The capability of MLIs became recognized as a significant aspect of a system heavily reliant on Pulse Width Modulation(PWM) strategy. The conventional high frequency PWM techniques suffer from significant Total Harmonic Distortion (THD) along with power loss difficulties. This work recommends a hybrid PWM technique for lowering the THD and power loss of VSI adding the benefits of level-shift PWM and Phase-shift PWM. A novel form of carrier signals is employed in the proposed hybrid PWM technique. In contrast to existing PWM techniques, the proposed hybrid PWM technique minimizes switching and conduction power losses. In this work, the proposed PWM scheme is employed for asymmetric multilevel inverter. The proposed configuration is also examined using PLECS software to estimate losses and efficiency. The simulation work is done in the MATLAB/Simulink environment and the OPAL-RT(OP4510) test platform is employed to evaluate topology performance.

New modified carrier-based level-shifted PWM control for NPC rectifiers considered for implementation in EV fast chargers

New modified carrier-based level-shifted PWM control for NPC rectifiers considered for implementation in EV fast chargers

An Analysis and Optimization of the Battery Capacity Difference Tolerance of the Modular Multi-Level Half-Bridge Energy Storage Converter

As a power converter of battery energy storage, the multi-level converter and its battery balancing control have received much attention from scholars. This paper focuses on the modular multi-level half-bridge energy storage converter (MMH-ESC), including its topology, working principle, and pulse width modulation (PWM) methods. Under the battery balancing control strategy based on level-shifted carrier PWM (LS-PWM), formulas are derived and calculations are performed to get the charge or discharge of each submodule (SM), thereby obtaining the tolerance for capacity differences among these batteries. A range of battery capacity values that can maintain a balanced state is provided to enhance flexibility in battery configuration and utilization, avoiding the limitation of all batteries to the same capacity. Finally, a new bridge arm modulation wave allocation method is proposed. This method significantly expands the range of SM battery capacity selection and provides a high-tolerance modulation method for the converter under extreme or even fault conditions.

Switched Capacitor Based Cascaded Half-Bridge Multilevel Inverter with Voltage Boosting Feature

Abstract: In many applications, cascading multilevel inverter (CMI) topologies are common. However, the biggest disadvantage of CMI is the need for many separate switches and DC sources. As a result, the CMI topology becomes more expensive, more complex, and larger, and its performance suffers. In the proposed SC-CHMI, only one DC source is used and the other DC sources are replaced by switched capacitor cells. Thanks to the self-balancing function, the capacitor charging process occurs naturally without the need for any auxiliary equipment. In the proposed SC-CHMI, the inrush current of the capacitor is attenuated using a load inductor or a front-end boost converter. To improve the performance of multi-level inverters, several types of techniques can be tested with existing multi-level inverters. Due to the modulation algorithm, modulation frequency, voltage drop on the switches and bus voltage modulation, the output voltage of the inverter has overall harmonic distortion, leading to overheating of the device and shortening the life of the device bag. In the proposed SC-CHMI, a level-shifted pulse width modulation technique is proposed to improve the output voltage quality and reduce the total harmonic distortion. This new control scheme is applicable to nine-level, eleven-level and fifteen-level SC-CHMI. The proposed topology can be used as a general-purpose inverter in renewable energy systems, due to its voltage gain characteristics, minimal number of switches, and single DC source. The effectiveness of the proposed inverter topology is confirmed by simulation results.

Switched capacitor based 7-level and 9-level multilevel inverters with single DC source and reduced voltage stress

This paper proposes two different switched capacitor based Multilevel Inverter topologies having single dc voltage source. One of the proposed MLIs is a seven-level structure whereas the other circuit successfully generates a nine-level output voltage. The special features of the seven-level topology consist of reduced number of circuit elements, lower voltage stress on switches, and boosted output voltage. The nine-level MLI having unity gain also possess the reduced switch count along with lower value of switch voltage stress. Fundamental frequency based Nearest Level Control modulation and Level-Shifted Pulse Width Modulation have been used for generating the required voltage levels. Successful implementation of the proposed MLI circuits has been done with the help of a laboratory prototype and its results are presented and explained in the paper to show its practical suitability. Other type of analysis include loss analysis which has been done in PLECS software. From this analysis, the efficiency has been estimated. A comparative analysis of both the proposed structures has been carried out with some other similar topologies on different performance parameters. From the analysis and comparison, it is evident that the proposed MLIs are better than some of the existing topologies and can be used for industrial applications.

Compact three‐phase multilevel inverter with boosting capability for low‐power three‐phase induction motor drive

SummaryThis paper proposes a step‐up three‐phase multilevel inverter based on switched capacitor (SC) cells. The prominent features of this inverter are the reduction of the number of components (such as switches, capacitors, and sources) and the ability to boost the voltage. Also, the self‐voltage balancing of the capacitors of this inverter is one of the other features of this inverter. The level‐shifted pulse width modulation (LS‐PWM) method has been used for switching, making the output currents' total harmonic distortion (THD) low. The article has presented the experimental results of this inverter with a three‐phase induction motor with a power of 1.1 kW as a load.

Efficiency of Series APF based on Nine-level NPC Inverter Compared to Seven-level Configuration

This article presents the performance comparison of Series Active Power Filter (Series APF) based on seven and nine multi-level Neutral Point Clamped (NPC) inverters using the same control scheme. The Series APF is one of the most efficient and effective modern custom power devices used in power distribution networks to compensate voltage harmonic and all voltage disturbances. The conventional configuration based on voltage source inverter (VSI) operated at very high switching frequency presents several drawbacks and limited for low power applications. To overcome these problems and improve the output voltage different multi-level are used in various power application in particular Flying Capacitor (FC), Cascade H-Bridge (CHB) and multi-level (NPC) inverters. In this study seven and nine-level (NPC) inverters are proposed for active power filtering system; these inverters present diverse advantages include the capability to reduce the harmonic content, decrease the voltage or current ratings of the semiconductors and mainly they can work at low switching frequency. To generate switching pulses Multi-Carrier Level-Shifted Pulse Width Modulation (MC-LSPWM) control technique is adopted with modified P-Q control strategies. To verify the accuracy and the performance of the proposed Series APF models, simulation is performed using MATLAB-Simulink platform and SimPowerSystem Toolbox. The obtained results show the superiority of series APF based on nine-level in term of THDv reduction compared to the systems with seven-level inverter topology.

Comparative performance of modular with cascaded H-bridge three level inverters

<span lang="EN-US">The conventional two-level inverter becomes no longer has the ability to cope with the high-power requirement, so this paper discusses two very common topologies of multilevel inverter like modular multi-level converter (MMC) and cascaded H-bridge (CHB) multi-level inverter for induction motor drive applications. This work attempts to investigate the comparison between MMC and CHB. The comparison is done in aspects of the configuration, concept of operation, advantages and disadvantages, the comparison is also consider output voltage (line to line) waveform, total harmonic distortion (THD) of the output line voltage waveform and the current drawn by both inverters. The performance of the inverters under carrier-based pulse width modulation (PWM) technique and mainly in-phase disposition (IPD), level shifted pulse width modulation is viewed. The paper discusses the comparison between the two multilevel inverters (MLIs) with motor drive applications especially induction motor. The operation of the motor is studied under certain value of load torque. The simulation results for the induction motor with the two inverters (modular multi-level and Cascaded H-bride) for three numbers of levels using MATLAB/Simulink are provided). The obtained results are encouraging and promising especially in the improvement of the THD% results.</span>

Self-Balanced Nine-Level Flying Capacitor Inverter With Double-Period Level-Shifted Control

Voltage imbalance and peak charging current often occurs in capacitor-containing inverters. To solve this problem, a nine-level flying capacitor inverter and a double-period level-shifted pulse-width modulation (DPLS-PWM) strategy is proposed. The proposed topology has the advantage of reduced capacitor count and low total standing voltage (TSV). Owing to the special redundant states of proposed inverter, a DPLS-PWM is introduced. By applying DPLS-PWM strategy, the two capacitors in the proposed inverter can be balanced naturally. Meanwhile, unlike most switched-capacitor (SC) inverters whose self-balance scheme often generate large inrush current, the current stress of the proposed balance scheme is low. The working modes of proposed inverter and the principles of DPLS-PWM is analyzed in detail. And comparisons are made to highlight the merits of the topology and modulation method. Simulation and experimental results have verified the feasibility of the proposed topology and self-balance modulation. The experimental efficiency of this inverter can reach over 98%.