Level-shifted Carrier Pulse Width Modulation Research Articles

An Analysis and Optimization of the Battery Capacity Difference Tolerance of the Modular Multi-Level Half-Bridge Energy Storage Converter

As a power converter of battery energy storage, the multi-level converter and its battery balancing control have received much attention from scholars. This paper focuses on the modular multi-level half-bridge energy storage converter (MMH-ESC), including its topology, working principle, and pulse width modulation (PWM) methods. Under the battery balancing control strategy based on level-shifted carrier PWM (LS-PWM), formulas are derived and calculations are performed to get the charge or discharge of each submodule (SM), thereby obtaining the tolerance for capacity differences among these batteries. A range of battery capacity values that can maintain a balanced state is provided to enhance flexibility in battery configuration and utilization, avoiding the limitation of all batteries to the same capacity. Finally, a new bridge arm modulation wave allocation method is proposed. This method significantly expands the range of SM battery capacity selection and provides a high-tolerance modulation method for the converter under extreme or even fault conditions.

A New Fault-Tolerant MLI—Investigating Its Skipped Level Performance

Generating higher voltage levels with fewer power electronic components and fault tolerance is a challenging issue for multilevel inverters (MLIs). In this article, a new generalized fault tolerant MLI (FTMLI) with reduced semiconductor switches is presented. The proposed FTMLI topology contains more redundant switching states; thus, the topology can tolerate faults in both switches and/or sources. This article also introduces the new level shifted carrier pulsewidth modulation technique in effective utilization of abnormal voltage level combinations (or skipped voltage level) for running emergency loads. The proposed topology's operation is discussed along with the fault-tolerant capability for both the symmetric and asymmetric modes. Experimental results are presented to show the effectiveness of the FTMLI topology using the associated control strategy. A comparative analysis between the proposed topology and other MLI topologies is also provided to highlight the proposed topology's merits.

Evaluation of level-shifted carrier PWM technique for neutral-point stabilisation of five-level DCMLI

The persistent issue with diode-clamped multilevel inverter is unbalance in DC-link capacitor voltages. These variations become predominant at load power factor near to unity. Evolved techniques exist to balance capacitor voltages for three-level inverter. But for the inverters above three level, the problem still persists. In this paper, a novel level-shifted carrier pulse width modulation technique is proposed. As per this technique, carriers are level shifted based on the difference in capacitor voltage and phase currents. This leads to variation in duty cycle of the switches and thereby adjusting the charging and discharging of capacitors to balance capacitor voltages. The proposed technique is mathematically modelled and verified for five-level inverter using MATLAB SIMULINK.

Comparison of Multicarrier PWM Techniques for Cascaded H-Bridge Multilevel Inverter

<p>One of the preferred choices of electronic power conversion for high power applications are multilevel inverters topologies finding increased attention in industry. Cascaded H-Bridge multilevel inverter is one of these topologies reaching the higher output voltage, power level and higher reliability due to its modular topology. Level Shifted Carrier Pulse Width Modulation (LSCPWM) and Phase Shifted Carrier Pulse Width Modulation are used generally for switching cascaded H-bridge (CHB) multilevel inverters. This paper compares LSCPWM and PSCPWM in terms of total harmonics distortion (THD) and output voltage among inverter cells. Simulation for 21-level CHB inverter is carried out in MATLAB/SIMULINK and simulation results are presented.</p>

Evaluating the capacity of power and energy balance for cascaded H‐bridge multilevel inverter using different PWM techniques

Among the different multilevel topologies for inverters, cascaded H-bridge multilevel topology has been a good solution for high-power medium-voltage applications because of its modularity structure, voltage balancing, separated DC sources, harmonics reduction, reliability and lower stresses on switching devices. The most widely used pulse width modulation (PWM) techniques for cascaded H-bridge multilevel inverter are known as phase shifted and level shifted. This study presents a comparison of power and energy distribution (inter-phase and inter-bridge power and energy) of three-phase cascaded H-bridge multilevel inverter for the phase-shifted and the level-shifted carrier PWM (phase disposition). A detailed comparison of different PWM techniques with reference to total harmonic distortion in the output voltages, both cases using a filter and without filter are presented also in this study. Simulation for 11-level cascaded H-bridge inverter is carried out in MATLAB/SIMULINK and simulation results are presented.

Novel carrier‐based hybrid pulse width modulation method for cascaded capacitor‐clamp multilevel inverter

This study presents a new carrier-based hybrid pulse width modulation (PWM) Method for the cascaded capacitor-clamp multilevel inverter (CCCMLI), which combines the benefits of a new alternative level-shifted carrier PWM and a phase-shifted carrier PWM. For modulating the CCCMLI, the phase disposition sub-harmonic PWM was first proposed, but does not show good performances in an even load sharing between inverter cells connected in series, flying-capacitor voltage balancing and output waveform quality. On the other hand, a proposed PWM method enables to achieve a balanced load sharing between cascaded cells even at low amplitude modulation indices as well as the excellent voltage balancing control of the flying-capacitors with a much smaller voltage ripple and the good harmonic characteristics in output waveforms. The proposed modulation is verified through both simulation and field-programmable gate array (FPGA) based experimental results.