Level Shifter Circuit Research Articles

Full-Swing Nanosecond Delay Hybrid Level Shifter for Time-Critical Applications

A crucial component of digital integrated circuits with numerous power domains is the level shifter (LS). The traditional topologies are currently the mirror LS and cross-coupled LS. For full-swing level conversions from extremely low voltage to the nominal voltage of the supply, ahybrid LS is proposed in this paper, which is a combination of the current mirror LS and cross-coupled LS with a swing-aware output inverter. The proposed LS circuit is designed to ensure full swing, static current-free, and limited current-contention level conversions by preserving the benefits of the current mirror and cross-coupled LS, and using them to eliminate each other’s shortcomings. The proposed hybrid LS is designed and implemented by using 45-nm technology in Cadence Virtuoso tool. Pass transistors and current limiters with multiple thresholds are included for the suggested LS. The proposed LS provides voltage conversion from 0.10 V to 1.20 V. At alevel-shifting voltage of 0.20 V, the proposed hybrid LS at 1 MHz input frequency demonstrates a delay of 8.38 ns, an average power consumption of 3.81 µW, and an energy per transition of 26.64 fJ. Additionally, the suggested LS has low delay, good supply voltage scaling, and delay scalability.

A 2.5–8V input range peak-current-control non-inverting buck-boost DC-DC converter with high efficiency and automatic mode transition for Ni-MH battery application

In portable electronic devices, the output voltage of the Ni-MH cell battery gradually decreases with the extension of run time, eventually leading to an inability to provide the required operating voltage. As a result, this paper proposed a non-inverting buck-boost converter with automatic switching of operating modes to extend the run time of Ni-MH batteries connected in series, which is peak current controlled. By comparing the input and output voltages, the DC-DC converter is placed in either buck, boost, or buck-boost mode. Of the three modes, the buck-boost mode is designed to have the smallest operating range due to its lowest power conversion efficiency. The converter is characterised by a wide input range of 2.5–8 V, which exceeds the maximum voltage leading to oxide breakdown. In order to prevent the breakdown of the gate oxide layer, a capacitive coupling level shift circuit is proposed to control voltage between gate and source of the power transistor below 5 V. The proposed converter is manufactured using a 180 nm BCD process and occupies an effective chip area of 1.44 mm × 0.73 mm. Experimental results demonstrate that the maximum power conversion efficiency of the proposed buck-boost DC-DC converter is 93%, marking a significant 11% enhancement compared to the traditional buck-boost DC-DC converter operating in only buck-boost mode (84% efficient). In addition, the converter achieves a maximum output current of 500 mA, which improves the output maximum current by 67% compared to the traditional DC-DC converter (max. output current 300 mA).

A Bootstrap Drive and Level Shifting Method for Buck-boost Converter with NMOS as the Main Switch Transistor

In the design of DC-DC power supply, compared with a P-type metal oxide semiconductor field effect transistor (PMOS) with the same width-to-length ratio, N-type metal oxide semiconductor field effect transistor (NMOS) as the main switching transistor greatly reduces the on-off loss and improves the conversion efficiency of the system. This article introduces a gate voltage bootstrap and level shifter circuit for a Buck-Boost DC-DC converter with NMOS main switching transistor. The drive voltage between the gate and the source pole of the main switch transistor can be stabilized, which is independent of the switch junction voltage (V SW) and solves the problem that the drive voltage of the gate is too high or too low due to the influence of the bootstrap voltage in the traditional structure. Based on the 0.18 μm BCD process, the circuit design and physical implementation of the proposed method are verified. The test results show that the bootstrap drive circuit functions normally and the bootstrap drive voltage is about 5 V when the input voltage is 2.9~4.5 V and the output voltage is −2~-5 V. In addition, the proposed gate-level shifting circuit can reduce the drive delay of the main switch transistor to less than 12 ns.

A Comprehensive Study on the Design Methodology of Level Shifter Circuits

The level shifter (LS) circuit has become an indispensable circuit component in both analog and digital systems. In the past decades, there has been an exponential increase in the academic publications for the LS circuits to improve their performances and their applications. Therefore, this review paper provides a comprehensive study of the LS circuit, ranging from circuit topologies and various design methodologies such as sizing methodology, layout design methodology, circuit evaluation methodology, and testing methodology. Finally, we evaluate the state-of-the-art LS circuits and present their performance metrics.

Design Of Voltage Level Shifter Using Regulated Cross Coupled Pull Up Networks

Level shifter plays an vital role in multiple supply voltage techniques which creates a path between processors, sensors or broads of different voltage levels, it converts the input logic levels or voltages below the VTH of the transistor to the higher acceptable levels depending upon the system requirements. So, it is necessary to design a level shifter circuit which provides high performance. Power consumption and delay are the key features which determines the performance of a level shifter. This project mainly focuses on designing the level shifter using regulated cross coupled pull up network which helps in utilizing less power and enhancing the speed of the circuit. The work carried out is the mini-project that is a part & parcel of the curriculum in the 2nd semester.

An Automatic Circuit Design Framework for Level Shifter Circuits

Although design automation is a key enabler of modern large-scale digital systems, automating the transistor-level circuit design process still remains a challenge. Some recent works suggest that deep learning algorithms could be adopted to find optimal transistor dimensions in relatively small circuitry such as analog amplifiers. However, those approaches are not capable of exploring different circuit structures to meet the given design constraints. In this work, we propose an automatic circuit design framework that can generate practical circuit structures from scratch as well as optimize the size of each transistor, considering performance and reliability. We employ the framework to design level shifter circuits, and the experimental results show that the framework produces novel level shifter circuit topologies and the automatically optimized designs achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.8\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.3\times $ </tex-math></inline-formula> lower power-delay product (PDP) than prior arts designed by human experts.

Physical Insights on Current Dynamics of RESURF DeMOS Designed for High-Frequency CMOS Level Shifter Application

This work investigates isothermal high-current dynamics of Drain-extended MOS (DeMOS) devices optimized for high-frequency switching applications. Gate charge optimized reduced-surface-field (RESURF) DeNMOS structures using surface-implant (P-Top) and split-gate (SG_NonSTI) have been compared with conventional DeNMOS (C_DeNMOS) to investigate the dynamics of parasitic BJT trigger and subsequent space charge modulation (SCM) under high current conditions. Comparative AC analysis at a different gate and drain bias shows quasi-saturation peaks responsible for space charge modulation under high current conditions in DeMOS devices. The transient analysis investigates the isothermal unclamped inductive switching (UIS) and reverse recovery behavior. The parasitic gate capacitances Cgg and Cgd are reduced in both P-Top and SG_NonSTI. With the lowest turn-off delay under very high current conditions in UIS simulations, SG_NonSTI shows the best switching reliability, while P-Top shows the best reverse recovery and transient switching delay performance. In addition, we have shown the application of proposed DeNMOS devices in designing a high-frequency CMOS level shifter circuit. Compared to C_DeNMOS, the highest operating frequency has increased for P-Top and SG_NonSTI DeNMOS structures by 40% and 35%, respectively.

Demonstration of integrate-and-fire neuron circuit for spiking neural networks

An integrate-and-fire (IF) neuron and a voltage level shifter circuit were fabricated and investigated for hardware-based SNN architectures. To verify an IF function of neurons, the fabricated IF neuron circuit consists of a synapse, an integration/reset part, and a fire/trigger circuit. By observing a membrane potential of the IF neuron circuit, an integration and reset operations are successfully implemented. In the fabricated IF neuron circuit, the number of output spikes is 2, 5, 10, and 20 at tpulses of 0.4 μs, 1 μs, 2 μs and 4 μs, respectively. The firing rate of the neuron circuit linearly increases as tpulse increases. These measurement results demonstrate that the fabricated IF neuron circuit implements IF function and reset operation well with linear activation function. For suppression of a gate induced drain leakage (GIDL) at high drain voltages (>6 V), the voltage level shifter consists of MOSFETs with a lightly doped drain (LDD). The generation of high voltage pulses (>6 V) for a synaptic weight update is observed through the voltage level shifter circuit.

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 μm CMOS technology occupies a silicon area of only 25 μm×25 μm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDL</sub> =0.8 V, and a capacitive load of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> =0.1 pF.

A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.

Design of low power SRAM- based ubiquitous sensor for wireless body area networks

Purpose Smart ubiquitous sensors have been deployed in wireless body area networks to improve digital health-care services. As the requirement for computing power has drastically increased in recent years, the design of low power static RAM-based ubiquitous sensors is highly required for wireless body area networks. However, SRAM cells are increasingly susceptible to soft errors due to short supply voltage. The main purpose of this paper is to design a low power SRAM- based ubiquitous sensor for healthcare applications. Design/methodology/approach In this work, bias temperature instabilities are identified as significant issues in SRAM design. A level shifter circuit is proposed to get rid of soft errors and bias temperature instability problems. Findings Bias Temperature Instabilities are focused on in recent SRAM design for minimizing degradation. When compared to the existing SRAM design, the proposed FinFET-based SRAM obtains better results in terms of latency, power and static noise margin. Body area networks in biomedical applications demand low power ubiquitous sensors to improve battery life. The proposed low power SRAM-based ubiquitous sensors are found to be suitable for portable health-care devices. Originality/value In wireless body area networks, the design of low power SRAM-based ubiquitous sensors are highly essential. This design is power efficient and it overcomes the effect of bias temperature instability.

Trends in Design of Low Power Circuits Using Level Shifting Buffers for Multi Supply Systems

Power and performance efficiencies are the most important design parameters in system – on - chip design. Numbers of methods were developed for reducing the power and delay by reducing supply voltage and multi supply voltages. Multiple supply voltage designs need voltage level conversions between multiple voltage domains. This is achieved by the application of voltage level shifter (LS) circuits. LSs are an interfacing circuit which interconnects low core voltage to high core voltage and vice versa. LS ease communication among diverse modules. However literature reported that the conventional LSs suffer from delay variation due to dissimilar current driving transistors along with high power dissipation. This paper presents the identification of limitations and design aspects of existing LSs through an extensive literature survey and to project the current state of LSs. This study concentrates on multiple supply voltages, power consumption, and speed of processing in ICs. The detailed literature review is expected to pave way for addressing the issues and challenges related to LSs and helps in design and development of efficient low-power multivoltage LSs in the design aspects of VLSI circuits.

Development of single channel EEG Acquisition system for BCI applications

Brain-Computer Interface (BCI) plays a major role in current technologies such as rehabilitation, control of devices, and various medical applications. BCI or brain-machine interface provides direct communication between a brain signal and an external device. In this paperwork, a detailed survey was carried out with the design of single-channel EEG system for various applications. Also, this paper mainly focused on the development of single-channel electroencephalography (EEG) signal acquisition system which includes a preamplifier, bandpass filter, post-amplifier and level shifter circuits. The design of the preamplifier and post-amplifier circuit was carried out by integrated circuits (IC) such as instrumentation amplifier IN128P and bandpass filter with the help of low power operational amplifier LM324. The developed single-channel acquisition board was tested by acquiring an electrooculogram (EOG) signal with closed and opened eye conditions. The acquired signal is displayed and stored in the computer with the help of the HBM-DAQ unit.

Preparation of a Simple Electrochemical Voltammetry Implementation System

Cyclic Voltammetry is an Electro-chemical process used in the development Energy Storage cells and general electrochemistry. In this report we present the use of an Atmega 326 microcontroller to prepare a Cyclic Voltammetry (CV) implementation system. The modular design incorporated a software pulse - width - modulated triangular wave generator, level shifter circuits, a three - electrode electrochemical tank driver circuit and PLX-DAQ-Excel digital Data Acquisition system. The system measured a 266.1 Ω carbon resistance as 262.7 Ω. It also effectively isolated the cathodic redox potential peak (750 mV) and anodic peak (520 mV) of a 1.5 mM Potassium Ferricyanide in 0.1M Potassium Nitrate at room temperature. A specific capacitance of 11.45 F/g was obtained for a 4.4 cm 2 coconut shell derived screen printed activated carbon electrode. The design is suitable for basic CV studies in Electrical Energy Storage Devices development. Keywords: Microcontroller, Cyclic Voltammetry, Potentiostat, Level – shifter circuits, Potassium ferricyanide, Energy Storage Devices. DOI: 10.7176/JNSR/12-18-04 Publication date: September 30 th 2021

High throughput SRAM design for improved computing in autonomous systems

PurposeHigh throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.Design/methodology/approachPower efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.FindingsBias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.Originality/valueThe proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

A Capacitorless and Low‐Optical‐Flicker AC Direct LED Driving IC and System Applied to Street Lighting

This study presents a novel alternating current (AC) direct light emitting diode (LED) driving integrated circuit (IC) and system applied to street lighting. In the proposed driving IC, the level shifter circuit is specially designed to enable it to be directly powered by the 380 V 50 Hz three‐phase AC, so that the characteristics of the three‐phase AC can be utilized to reduce the harmful optical flicker and increase the output power of the driving system. And a new power factor correction circuit is proposed to improve the power factor of the driving IC. In addition, the power compensation circuit with negative feedback is designed to stabilize the average output power when the voltage of the power grid fluctuates. The driving IC and system are fabricated with a 1 μm 700 V Bipolar‐CMOS‐DMOS process. The driving system does not need electrolytic capacitors, achieves 72 W output power and an up to 0.993 PF with only 12.7% percent flicker at the 380 V 50 Hz three‐phase AC input, while the frequency of the output power is improved to 300 Hz, and the average output power varies only from −2.3% to 0.7% with the help of the power compensation circuit. © 2021 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers

This brief presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitive-coupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 μm HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of dV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SSF</sub> /dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> and FoM <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

Power‐efficient voltage up level shifter with low power–delay product

SummaryIn this article, a power‐efficient hybrid voltage up level shifter (LS) is designed. By using a combination of a current mirror (CM) and a cross‐coupled pMOS pair in a pull‐up circuitry, the dynamic power is reduced significantly even at boosted switching speed. The designed LS circuit, which occupies a small silicon area, consists of 10 transistors and is mainly suitable for ultra‐low‐power applications, such as wireless sensor nodes and biomedical appliances. Moreover, it can convert extreme low‐level input voltages to the high supply voltage levels. The results obtained from post‐layout simulations in a standard 180‐nm CMOS process illustrate that the designed LS circuit has total power consumption, static power dissipation, and propagation delay of 33.93 nW, 253 pW, and 9.09 ns, respectively, at 1 MHz with a minimum supply voltage (VDDL) of 0.4 V and nominal supply voltage (VDDH) of 1.8 V. Also, the designed LS can convert an input voltage of 0.12–1.8 V at 10 kHz.

An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique

The increasing number of voltage domains along with the size of the data bus requires an exponential increase in the number level shifter (LS) circuits for signal interfacing, creating an exploding in silicon area and power consumption. Higher area-efficiency can be attained by further improving the integration density of the LS circuit. In this paper, we present a multi-function ultra-low-voltage LS with re-configurable logic with embedded time-borrowing latch. The proposed circuit is implemented on CMOS 45nm technology. It is capable of converting the input voltage of 0.3 V to an output voltage of 1.8 V with an input frequency of 1 MHz. The proposed architecture has achieved a superior area efficiency with reduced transistors number of $2.4\times $ and reduced power delay product (PDP) of $4.65\times $ compared with its discrete logic block level implementation when the input voltage, output voltage, and the input frequency are 0.3 V, 1.8 V, and 1 MHz, respectively. The average propagation delay and power consumption are 52.7 ns and 34.6 nW, respectively.

Performance analysis of multi-scaling voltage level shifter for low-power applications

Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.