Level Programming Model Research Articles

Multi-target Programming Method for Active Distribution Network Considering the Multiple Collaborative Interaction Effect

The effect of indeterminacy of distributed generation should be fully considered in the planning of active distribution network. Based on the conventional load forecasting, the trusted output model of distributed generation connected to active distribution network is built. Thinking the influence of load demand side response on the forecasted load results, a distribution network load forecasting model considering the multiple synergistic interaction effect of source, load and storage is proposed. Based on the results of load forecasting, a double-deck multi-objective programming model of active distribution network is established. The upper deck function is the problem of power grid optimization planning, and the goal is to minimize the annual network comprehensive cost; The lower level programming model determines the active power output of manageable resources such as energy stored based on the typical daily system operation economy under the grid achieved by the upper part planning. Through the optimization solution, the distribution network planning scheme and the location and capacity scheme of energy storage under the active management mode are obtained. In result, we use an active distribution network in Shanghai to prove the scientificity and effectiveness of the proposed programming method

Investigation of Climate Change Adaptation Impacts on Optimization of Water Allocation Using a Coupled SWAT-bi Level Programming Model

One way to deal with the future effects of climatic changes on the water resources and to cope with water shortages in basins is to have a clear understanding of the future climate change trends. To this end, this study proposes an integrated hydrological-water transfer and supply (HWTS) framework including a coupled SWAT-Bi level programming model to investigate future optimal water supply between different sectors with regard to transaction right. Indeed, Soil & Water Assessment Tool (SWAT) is applied to project the rate of streamflow under Representative Concentration Pathway scenarios of RCP2.6&RCP4.5 and future periods (2020–2040 & 204(Abbas et al. 2015)2060). In addition, a case study of the Hamoun wetland in southeastern of Iran is considered for calibration and validation of real historical data (2000–2016) and then simulation of future streamflow patterns (2020–2060). Next, simulated streamflow data extracted by SWAT is entered as the input of market based bi-level optimization model so that upper-level manager seeks optimization of the available water level in the reservoirs while the lower-level decision maker tries to minimize the economic loss due to water shortage between different sectors regarding transaction right. However, after solving the model with the Improved Particle Swarm Optimization (IBPSO) technique, the final results show that although not much economic profit will be made, but considering specific management strategies such as demand reduction schemes to conserve more water, the imbalance between supply and demand can be significantly improved.

PICO: A platform independent communications middleware for heterogeneous devices in smart grids

This paper presents a data-centric middleware responsible for real-time communication and data storage in smart grids. The middleware offers a high level programming model that provides ways of storing/getting information from/to the grid and encrypts messages thus providing a secure message exchange. The design has taken into account the heterogeneity of devices, software platforms and stakeholders involved in this kind of Cyber-physical System (CPS). A modular vision is followed in such a way that middleware components can be easily adapted to different platforms and a simple data interface is provided by using REST (Representational State Transfer) web services and a high level asynchronous API. The middleware has been used in the context of a European project (e-balance) where soft real-time requirements, security and low capacity devices were some of the requirements. The demonstration scenarios are detailed in this paper together with the validation tests that show that the use of this programming abstraction is feasible.

OpenACC Errors Classification and Static Detection Techniques

With the continued increase of usage of High-Performance Computing (HPC) in scientific fields, the need for programming models in a heterogeneous architecture with less programming effort has become important in scientific applications. OpenACC is a high-level parallel programming model used with FORTRAN, C, and C++ programming languages to accelerate the programmers' code with fewer changes and less effort, which reduces programmer workloads and makes it easier to use and learn. Also, OpenACC has been increasingly used in many top supercomputers around the world, and three of the top five HPC applications in Intersect360 Research are currently using OpenACC. However, when programmers use OpenACC to parallelize their code without correctly understanding OpenACC directives and their usage or following OpenACC instructions, they can cause run-time errors that vary from causing wrong results, performance issues, and other undefined behaviors. In addition, building parallel systems by using a higher level programming model increase the possibility to introduce errors, and the parallel applications thus have non-determined behavior, which makes testing and detecting their run-time errors a challenging task. Although there are many testing tools that detect run-time errors, this is still inadequate for detecting errors that occur in applications implemented in high-level parallel programming models, especially OpenACC related applications. As a result, OpenACC errors that cannot be detected by compilers should be identified, and their causes should be explained. In this paper, our contribution is introducing new static techniques for detecting OpenACC errors, as well as for the first time classifying errors that can occur in OpenACC software programs. Finally, to the best of our knowledge, there is no published work to date that identifies or classifies OpenACC-related errors, nor is there a testing tool designed to test OpenACC applications and detect their run-time errors.

Optimal Allocation of Intermittent Distributed Generation under Active Management

In recent years, distributed generation (DG) has developed rapidly. Renewable energy, represented by wind energy and solar energy, has been widely studied and utilized. At present, most distributed generators follow the principle of “installation is forgetting” after they are connected to a distribution network. This principle limits the popularization and benefit of distributed generation to a great extent. In order to solve these problems, this paper presents a two-tier model for optimal allocation of distributed power sources in active distribution networks (ADN). The objective of upper level planning is to minimize the annual comprehensive cost of distribution networks, and the objective of lower level planning is to minimize the active power cut-off of distributed generation through active management mode. Taking into account the time series characteristics of load and distributed power output, the improved K-means clustering method is used to cluster wind power and the photovoltaic output in different scenarios to get the daily curves in typical scenarios, and a bilevel programming model of distributed generation based on multiscenario analysis is established under active management mode. The upper level programming model is solved by Quantum genetic algorithm (QGA), and the lower level programming model is solved by the primal dual interior point method (PDIPM). The rationality of the model and the effectiveness of the algorithm are verified by simulation and analysis of a 33-bus distribution network.

A visual programming framework for distributed Internet of Things centric complex event processing

Complex Event Processing (CEP) is a promising approach for real-time processing of big-data streams originating from Internet of Things (IoT) devices. Even though scalability and flexibility are key issues for IoT applications, current studies are mostly based on centralized solutions and restrictive query languages. Moreover, development, deployment and operation of big-data applications require significant amount of technical expertise. Hence, a framework that provides a higher abstraction level programming model and a streamlined execution environment is essential to facilitate widespread user adoption. In this paper, we propose a data-flow based visual programming model that enables development of big-data applications in IoT domain even by users who have limited or no experience in big-data technologies. A scalable CEP engine is also devised to execute the applications developed using this language. A prototype is implemented by using the state-of-the-art big-data and real-time stream processing technologies to evaluate the applicability and usability of the framework.

Transit Network Design Based on the Bi-Level Programming

In this work, we study the transit network design problem on the basis of present urban road network from the perspective of programming and optimizing. So we propose a bi-level programming model to design the transit network. Considering the generation of bus lines, the number of stops along the lines, the interval of departing time, the number of buses on each line every day and so on, planners make endeavors to minimize running cost of transit system in the upper programming model. The lower level programming model is mainly from the angle of the travelers, taking travel time that is also called general travel cost, including in-vehicle travel time and transfer time, as the optimization goal. Finally, a simple experiment is performed to demonstrate the efficiency of the bi-level model above.

Pragma Directed Shared Memory Centric Optimizations on GPUs

GPUs become a ubiquitous choice as coprocessors since they have excellent ability in concurrent processing. In GPU architecture, shared memory plays a very important role in system performance as it can largely improve bandwidth utilization and accelerate memory operations. However, even for affine GPU applications that contain regular access patterns, optimizing for shared memory is not an easy work. It often requires programmer expertise and nontrivial parameter selection. Improper shared memory usage might even underutilize GPU resource. Even using state-of-the-art high level programming models (e.g., OpenACC and OpenHMPP), it is still hard to utilize shared memory since they lack inherent support in describing shared memory optimization and selecting suitable parameters, let alone maintaining high resource utilization. Targeting higher productivity for affine applications, we propose a data centric way to shared memory optimization on GPU. We design a pragma extension on OpenACC so as to convey data management hints of programmers to compiler. Meanwhile, we devise a compiler framework to automatically select optimal parameters for shared arrays, using the polyhedral model. We further propose optimization techniques to expose higher memory and instruction level parallelism. The experimental results show that our shared memory centric approaches effectively improve the performance of five typical GPU applications across four widely used platforms by 3.7x on average, and do not burden programmers with lots of pragmas.

Bi-Level Programming of Urban Bus Stop Selection

By using the system analysis method. and game theory of governmental placement of urban bus stops, operation of transit enterprises, and travelers' choice of trip mode, transit line, and bus stop location, the research objectives of this study are to solve the bi-Ievel programming problem for optimized urban bus stop placement with elastic demand and to establish a bi­ level programming model. The upper-level goal of the government and transit enterprises for choosing bus stops from possible se­ lections is to minimize travelers'total travel cost, to minimize bus operating cost, and to maximize the bus trip volume. The low­ er-level goal of the traveler for choosing travel mode, transit lines, and final bus stop is to minimize his generalized cost within equilibrium of the traffic assignment. A genetic algorithm is adopted in the concrete optimization solution. The game analysis of different decision agents and the concrete restriction of bus stop location are considered using the bi-Ievel programming method for ultimate selection of the bus stops. Moreover, the feasibility and correctness of the method. are proved.

Park-and-Ride Network Design: A Goal Programming Approach

The paper addresses a park and ride network design problem in a bi-model transport network in a multi-objective decision making framework. A goal programming approach is adopted to solve the multi-objective park and ride network design problem. The goal programming approach considers the user-defined goals and priority structure, which are (i) traffic-efficient goal, (ii) total transit usage goal, (iii) spatial equity goal. This problem is formulated as a bi-level programming model. The upper level programming leads to minimize the deviation from stated goals in the context of a given priority ranking. While the lower level programming model is a modal split/traffic assignment model which is used to assess any given park and ride scheme. A heuristic tabu search algorithm is then adopted to solve this model.

Network Design of Park-and-Ride System to Promote Transit Patronage

This paper proposed a bi-level programming model to optimize the locations and capacity for rail-based park-and-ride sites to promote transit patronage. A multinomial logit model was incorporated in a mode split/traffic assignment model to assess any given park-and-ride scheme. This model was then taken as the lower level model, and the upper level programming model is established to optimize the location and capacity of park-and-ride with the goal of promoting transit patronage. A heuristic tabu search algorithm is then adopted to solve this model.

Research on Air Transportation Network with Information Technology for Express Logistics Enterprise

Air transportation network reasonable planning related to express the long-term development of the enterprise, optimized air transportation network can make the express enterprises with strong market competitiveness. Based on the induction, and summarized the domestic and foreign related research results of air transportation network, and the importance of long-term development of enterprises, this paper shows the "air transport hub" bi level programming model and algorithm. EMS is an example.

Performance of CPU/GPU compiler directives on ISO/TTI kernels

GPUs are slowly becoming ubiquitous devices in High Performance Computing, as their capabilities to enhance the performance per watt of compute intensive algorithms as compared to multicore CPUs have been identified. The primary shortcoming of a GPU is usability, since vendor specific APIs are quite different from existing programming languages, and it requires a substantial knowledge of the device and programming interface to optimize applications. Hence, lately a growing number of higher level programming models are targeting GPUs to alleviate this problem. The ultimate goal for a high-level model is to expose an easy-to-use interface for the user to offload compute intensive portions of code (kernels) to the GPU, and tune the code according to the target accelerator to maximize overall performance with a reduced development effort. In this paper, we share our experiences of three of the notable high-level directive based GPU programming models--PGI, CAPS and OpenACC (from CAPS and PGI) on an Nvidia M2090 GPU. We analyze their performance and programmability against Isotropic (ISO)/Tilted Transversely Isotropic (TTI) finite difference kernels, which are primary components in the Reverse Time Migration (RTM) application used by oil and gas exploration for seismic imaging of the sub-surface. When ported to a single GPU using the mentioned directives, we observe an average 1.5---1.8x improvement in performance for both ISO and TTI kernels, when compared with optimized multi-threaded CPU implementations using OpenMP.

PS-QUASAR: A publish/subscribe QoS aware middleware for Wireless Sensor and Actor Networks

It has been more than 30 years since the first research into Wireless Sensor and Actor Networks appeared. However, WSANs are still not a ubiquitous technology due to several factors which include a lack of Quality of Service (QoS) support or the absence of high level programming models. New applications with heterogeneous QoS requirements where WSANs can be successfully applied, such as Critical Infrastructure Protection (CIP), have been recognized.PS-QUASAR, a middleware for WSANs that deals with these two issues, offers a high level simple programming model based on the publish/subscribe paradigm. In this model all nodes in the network are potential publishers of each of the topics. PS-QUASAR also handles QoS (reliability, deadline, priority) and supports a many-to-many exchange of messages between nodes in a fully distributed way by means of multicasting techniques. Performance evaluation via simulation using the Contiki operating system shows that the protocol can handle multiple publishers and subscribers at the same time whilst dealing with QoS requirements.

Efficient implementation of data flow graphs on multi-gpu clusters

Nowadays, it is possible to build a multi-GPU supercomputer, well suited for implementation of digital signal processing algorithms, for a few thousand dollars. However, to achieve the highest performance with this kind of architecture, the programmer has to focus on inter-processor communications, tasks synchronization. In this paper, we propose a high level programming model based on a data flow graph (DFG) allowing an efficient implementation of digital signal processing applications on a multi-GPU computer cluster. This DFG-based design flow abstracts the underlying architecture. We focus particularly on the efficient implementation of communications by automating computation–communication overlap, which can lead to significant speedups as shown in the presented benchmark. The approach is validated on three experiments: a multi-host multi-gpu benchmark, a 3D granulometry application developed for research on materials and an application for computing visual saliency maps.

Providing Source Code Level Portability Between CPU and GPU with MapCG

Graphics processing units (GPU) have taken an important role in the general purpose computing market in recent years. At present, the common approach to programming GPU units is to write GPU specific code with low level GPU APIs such as CUDA. Although this approach can achieve good performance, it creates serious portability issues as programmers are required to write a specific version of the code for each potential target architecture. This results in high development and maintenance costs. We believe it is desirable to have a programming model which provides source code portability between CPUs and GPUs, as well as different GPUs. This would allow programmers to write one version of the code, which can be compiled and executed on either CPUs or GPUs efficiently without modification. In this paper, we propose MapCG, a MapReduce framework to provide source code level portability between CPUs and GPUs. In contrast to other approaches such as OpenCL, our framework, based on MapReduce, provides a high level programming model and makes programming much easier. We describe the design of MapCG, including the MapReduce-style high-level programming framework and the runtime system on the CPU and GPU. A prototype of the MapCG runtime, supporting multi-core CPUs and NVIDIA GPUs, was implemented. Our experimental results show that this implementation can execute the same source code efficiently on multi-core CPU platforms and GPUs, achieving an average speedup of 1.6 ~ 2.5x over previous implementations of MapReduce on eight commonly used applications.

Language virtualization for heterogeneous parallel computing

As heterogeneous parallel systems become dominant, application developers are being forced to turn to an incompatiblemix of low level programming models (e.g. OpenMP, MPI, CUDA, OpenCL). However, these models do little to shield developers from the difficult problems of parallelization, data decomposition and machine-specific details. Most programmersare having a difficult time using these programming models effectively. To provide a programming modelthat addresses the productivity and performance requirements for the average programmer, we explore a domainspecificapproach to heterogeneous parallel programming. We propose language virtualization as a new principle that enables the construction of highly efficient parallel domain specific languages that are embedded in a common host language. We define criteria for language virtualization and present techniques to achieve them.We present two concrete case studies of domain-specific languages that are implemented using our virtualization approach.

A Case Study for NoC-Based Homogeneous MPSoC Architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processor.

Parallel Programming of Multi-processor SoC: A HW–SW Interface Perspective

For the design of classic computers the parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to existing multiprocessor platforms using a low level software layer that implements the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hard-ware and software refinements. This paper deals with parallel programming models to abstract both hardware and software interfaces in the case of heterogeneous MPSoC design. Different abstraction levels will be needed. For the long term, the use of higher level programming models will open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs.

Towards a general framework for FPGA based image processing using hardware skeletons

In this paper, we present our approach to developing a general framework for FPGA based Image Processing. This framework is based on a library of hardware skeletons. A hardware skeleton is a parameterised description of a task-specific architecture. A skeleton's implementation will apply optimisations specific to the target hardware. The library normally contains a range of alternative skeletons for the same task, perhaps tailored for different data representations. The library also contains high level skeletons for compound operations, whose implementation can apply appropriate optimisations. Given a complete algorithm description in terms of skeletons, an efficient hardware configuration is generated automatically. We have developed a library of hardware skeletons for common image processing tasks, with optimised implementations specifically for Xilinx XC4000 FPGAs. This paper presents and illustrates our hardware skeleton approach in the context of some common image processing tasks. It demonstrates our approach to the broader problem of achieving optimised hardware configurations while retaining the convenience and rapid development cycle of an application-oriented, high level programming model.