Length Low-density Parity-check Research Articles

Girth aware normalized min sum decoding algorithm for shorter length low density parity check codes

Recently, short block codes are in great demand due to the emergent applications requiring the transmission of a short data unit and can guarantee speedy communication, with a minimum of latency and complexity which are among the technical challenges in today’s wireless services and systems. In the context of channel coding using low density parity check (LDPC) codes, the shorter length LDPC block codes are more likely to have short cycles with lengths of 4 and 6. The effect of the cycle with the minimum size is that this one prevents the propagation of the information in the Tanner graph during the iterative process. Therefore, the message decoded by short block code is assumed to be of poor quality due to short cycles. In this work, we present a study of the evolution of the messages on check nodes during the iterative decoding process when using the LDPC decoding algorithm normalized min sum (NMS), to see the destructive effect of short cycles and justify the effectiveness of the girth aware normalized min sum (GA-NMS) decoding LDPC codes algorithm in terms of correction of the errors, particularly for the codes with short cycles 4 and 6. In addition to this, the GA-NMS algorithm is evaluated in terms of bit error rate performance and convergence behavior, using wireless regional area networks (WRAN) LDPC code, which is considered as a short block code.

Low Complexity Generalized-LDPC Decoder Based on Trellis Splicing

The high reliability short length low-density parity-check (LDPC) codes for Ultra Reliable Low Latency Communication (URLLC) are particularly important to future wireless communication systems. Even though the error floor region performance can be improved by using generalized-LDPC (G-LDPC) decoder, its penalty of increasing complexity can not be ignored. In this letter, we invoke the early stop criterion and the trellis splicing (TS) method to G-LDPC decoder. Hence, a G-LDPC-TS decoder is proposed. The proposed method can effectively reduce the number of variable nodes (VNs) involved in BCJR (Bahl-Cocke-Jelinek-Raviv) decoding of G-LDPC; thus, it yields a lower computational complexity. The results confirm that our G-LDPC-TS decoder can achieve a significant complexity reduction without sacrificing the performance.

Modified Min Sum Decoding Algorithm for Low Density Parity Check Codes

Abstract The Sum Product Algorithm (SPA) is known to offer the best performance in decoding large block length Low Density Parity Check (LDPC) codes. However, modifications in SPA to decrease the computation complexity have resulted in performance degradation. The Min Sum Algorithm (MSA) is one such variant, where the computation of the check-to-variable message is simplified to a minimum operation, instead of a hyperbolic tan calculation. Several modifications have been proposed in order to recover the performance loss of the MSA with respect to SPA. This paper proposes a modification to the MSA, based on the Wiener and Linear Minimum Mean Square Error (LMMSE) estimators for LDPC codes. The golden section search algorithm has been used to optimize the computations of the parameter estimation. Simulation results with these estimated parameters show that for low values of SNR, the modified algorithm outperforms MSA and provides performance close to that of SPA with a gain of 0.1 dB. For higher values of SNR, it outperforms MSA with a gain of 1.75 dB while providing an acceptable performance degradation with respect to SPA.

Iterative Detection and Decoding for Large-Scale Multiple-Antenna Systems With 1-Bit ADCs

We present a novel iterative detection and decoding scheme for uplink large-scale multiuser multiple-antenna systems. In order to reduce the receiver’s energy consumption and computational complexity, 1-bit analog-to-digital converters are used in the front-end. The performance loss due to the 1-bit quantization can be mitigated by using large-scale antenna arrays. We propose a linear low-resolution-aware minimum mean square error detector for soft multiuser interference mitigation. Moreover, short block length low-density parity-check codes are considered for avoiding high latency. In the channel decoder, a quasi-uniform quantizer with scaling factors is devised to lower the error floor of low-density parity-check codes. Simulations show good performance of the system in terms of bit error rate as compared to prior work.

Bit Mapping Design for LDPC Coded BICM Schemes With Multi-Edge Type EXIT Chart

In this letter, we consider the bit mapping (BM) design for regular low-density parity-check (LDPC) coded bit-interleaved coded modulation (BICM) schemes. We propose a check-node type distribution and develop multi-edge type extrinsic information transfer (EXIT) functions for the regular LDPC coded BICM schemes. Based on the EXIT functions, we propose a two-phase design method to generate the optimized practical BM in terms of the lowest decoding threshold for a given finite length LDPC code. Simulation results show that the proposed BM has a better decoding threshold compared with those of the existing works.

CS image reconstruction by novel small length LDPC code

Compressed sensing (CS) is capable of reconstructing the data signal from very small number of measurements. However the reconstructed image quality gets highly affected in the case of far end reconstruction involving transmission through a channel. In this work, a novel small length binary low density parity check (LDPC) code for far-end transmission of compressively sampled signals is proposed. Smaller length of LDPC code means faster computation. Also the code rate of proposed LDPC code is constructed to be 0.6 as in an earlier work by the same group it has been demonstrated that quasi-cyclic LDPC codes, with code rate 0.67 gives optimum performance with CS. The proposed code has a base matrix of size 4 × 10. The length of the LDPC code constructed, can be adjusted by a base matrix multiplying factor. The multiplying factor varies from 10 to 30 in steps of 4. The constructed code has a variable length between 100 and 300, in steps of 40. Simulation results of the proposed LDPC code show good performance when decoded iteratively by min-sum decoding algorithm. The proposed LDPC code also gives improved CS reconstruction for far end reconstruction.

High-efficiency Gaussian key reconciliation in continuous variable quantum key distribution

Efficient reconciliation is a crucial step in continuous variable quantum key distribution. The progressive-edge-growth (PEG) algorithm is an efficient method to construct relatively short block length low-density parity-check (LDPC) codes. The qua-sicyclic construction method can extend short block length codes and further eliminate the shortest cycle. In this paper, by combining the PEG algorithm and qua-si-cyclic construction method, we design long block length irregular LDPC codes with high error-correcting capacity. Based on these LDPC codes, we achieve high-efficiency Gaussian key reconciliation with slice recon-ciliation based on multilevel coding/multistage decoding with an efficiency of 93.7%.

Comparison of Convolutional and Block Codes for Low Structural Delay

The performance of short block length low-density parity-check (LDPC) codes (both binary and nonbinary) and convolutional codes is compared under the constraint of tight structural delay constraints. Additionally, we use fundamental bounds on block codes and low rate turbo codes to evaluate our results in a broader context. It turns out that—depending on the code rate and given delay—convolutional codes are able to outperform fundamental lower bounds for block codes, yielding a definite result on the question, which codes are superior in this regime. From a break-even point onward, convolutional codes cannot compete with block codes anymore and nonbinary LDPC codes show the best performance. Turbo codes with a short interleaver length show competitive results.

On Efficient Design of LDPC Decoders for Wireless Sensor Networks

Low density parity check (LDPC) codes are error-correcting codes that offer huge advantages in terms of coding gain, throughput and power dissipation in digital communication systems. Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However,traditional hardware implementation of LDPC decoders require large amount of resources, rendering them unsuitable for use in energy constrained sensor nodes of wireless sensor networks (WSN). This paper investigates the use of short-length LDPC codes for error correction in WSN. It presents the LDPC decoder designs, implementation, resource requirement and power consumption to judge their suitability for use in the sensor nodes of WSN. Due to the complex interconnections among the variable and check nodes of LDPC decoders, it is very time consuming to use traditional hardware description language (HDL) based approach to design these decoders. This paper presents an efficient automated high-level approach to designing LDPC decoders using a collection of high-level modelingtools. The automated high-level design methodology provides a complete design flow to quickly and automatically generate, test and investigate the optimum (length) LDPC codes for wireless sensor networks to satisfy the energy constraints while providing acceptable bit-error-rate performance.

Blind reconciliation

Information reconciliation is a crucial procedure in the classical post-processing of quantum key distribution (QKD). Poor reconciliation efficiency, revealing more information than strictly needed, may compromise the maximum attainable distance, while poor performance of the algorithm limits the practical throughput in a QKD device. Historically, reconciliation has been mainly done using close to minimal information disclosure but heavily interactive procedures, like \textit{Cascade}, or using less efficient but also less interactive ---just one message is exchanged--- procedures, like the ones based in low-density parity-check (LDPC) codes. The price to pay in the LDPC case is that good efficiency is only attained for very long codes and in a very narrow range centered around the quantum bit error rate (QBER) that the code was designed to reconcile, thus forcing to have several codes if a broad range of QBER needs to be catered for. Real world implementations of these methods are thus very demanding, either on computational or communication resources or both, to the extent that the last generation of GHz clocked QKD systems are finding a bottleneck in the classical part. In order to produce compact, high performance and reliable QKD systems it would be highly desirable to remove these problems. Here we analyse the use of short-length LDPC codes in the information reconciliation context using a low interactivity, \textit{blind}, protocol that avoids an a priori error rate estimation. We demonstrate that $2 \times 10^3$ bits length LDPC codes are suitable for blind reconciliation. Such codes are of high interest in practice, since they can be used for hardware implementations with very high throughput.

45 Gb/s low complexity optical front-end for soft-decision LDPC decoders

In this paper a low complexity and energy efficient 45 Gb/s soft-decision optical front-end to be used with soft-decision low-density parity-check (LDPC) decoders is demonstrated. The results show that the optical front-end exhibits a net coding gain of 7.06 and 9.62 dB for post forward error correction bit error rate of 10(-7) and 10(-12) for long block length LDPC(32768,26803) code. The performance over a hard decision front-end is 1.9 dB for this code. It is shown that the soft-decision circuit can also be used as a 2-bit flash type analog-to-digital converter (ADC), in conjunction with equalization schemes. At bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) used with a 6-tap finite impulse response (FIR) equalizer will result in optical power savings of 3, 5, 7, 9.5 and 10.5 dB, respectively. The 2-bit flash ADC consumes only 2.71 W at 32 GSamples/s. At 45 GSamples/s the power consumption is estimated to be 4.95 W.

Low-Density Parity-Check Coding in Ultra-Wideband-Over-Fiber Systems

In this letter, the performance of an ultra-wideband (UWB)-over-fiber system with low-density parity-check (LDPC) coding is experimentally investigated and supported by a simulation study. The results show that short block length LDPC coding provides a coding gain between 5.75 and 8.5 dB for a code rate of 50% and 93.3%, respectively, compared to an uncoded UWB-over-fiber system at a bit-error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> after error correction.

Analytical Solution of Covariance Evolution for Irregular LDPC Codes

The scaling law developed by Amraoui et al. is a powerful technique to estimate the block erasure probabilities of finite- length low-density parity-check (LDPC) codes. Solving a system of differential equations called covariance evolution, one can obtain the scaling parameter. However, the covariance evolution has not been analytically solved. In this paper, we present the analytical solution of the covariance evolution for irregular LDPC code ensembles.

Optimization of Construction and Encoding for Finite Length Irregular LDPC Codes

The main influence for the performance of finite length Low-Density Parity-Check(LDPC) codes is analyzed. According to optimum choice for degree distribution, a check matrix is constructed with improved Progressive-Edge-Growth (PEG) algorithm. A practical efficient encoding algorithm is proposed to optimize the check matrix. A finite length irregular LDPC code with low error-floor performance and approximate linear encoding complexity is obtained. This optimization method can be easily extended to general communication channels.

Novel modified min-sum decoding algorithm for low-density parity-check codes

The problem of improving the performance of min-sum decoding of low-density parity-check (LDPC) codes is considered in this paper. Based on min-sum algorithm, a novel modified min-sum decoding algorithm for LDPC codes is proposed. The proposed algorithm modifies the variable node message in the iteration process by averaging the new message and previous message if their signs are different. Compared with the standard min-sum algorithm, the modification is achieved with only a small increase in complexity, but significantly improves decoding performance for both regular and irregular LDPC codes. Simulation results show that the performance of our modified decoding algorithm is very close to that of the standard sum-product algorithm for moderate length LDPC codes.

Multistep Linear Programming Approaches for Decoding Low-Density Parity-Check Codes

The problem of improving the performance of linear programming (LP) decoding of low-density parity-check (LDPC) codes is considered in this paper. A multistep linear programming (MLP) algorithm was developed for decoding LDPC codes that includes a slight increase in computational complexity. The MLP decoder adaptively adds new constraints which are compatible with a selected check node to refine the results when an error is reported by the original LP decoder. The MLP decoder result is shown to have the maximum-likelihood (ML) certificate property. Simulations with moderate block length LDPC codes suggest that the MLP decoder gives better performance than both the original LP decoder and the conventional sum-product (SP) decoder.

Performance Bound for LDPC Coded Unitary Space–Time Modulation

This paper is concerned with the bit error probability (BEP) of coded unitary space---time modulation systems based on finite-length low density parity check (LDPC) codes. The union bound on the BEP of the maximum likelihood (ML) decoding is derived for any code rate, unitary space---time constellation and mapping. The tightness of the bound is checked with simulation results of the ordered statistic decoding (OSD). Numerical and simulation results show that the union bound is also close to the error performance of the sum---product (SP) decoding at low BEP levels when Gray mapping is employed. The derived bound is useful to benchmark the error performance of finite-length coded unitary space---time modulation systems, especially for those that employ short-to-medium length LDPC codes.

Stochastic decoding of LDPC codes

This letter presents the first successful method for iterative stochastic decoding of state-of-the-art low-density parity-check (LDPC) codes. The proposed method shows the viability of the stochastic approach for decoding LDPC codes on factor graphs. In addition, simulation results for a 200 and a 1024 length LDPC code demonstrate the near-optimal performance of this method with respect to sum-product decoding. The proposed method has a significant potential for high-throughput and/or low complexity iterative decoding.

Low Complexity MIMO-LDPC CDMA Systems over Multipath Channels

This paper proposes a low complexity composite CDMA system based on MIMO (Multiple-Input-Multiple-Output) processing and LDPC (low-density parity-check) codec based a CDMA system, which works well even if the complicated case of multipath, multiusers and short length LDPC codes. To explore the practical application, the mobile user in the composite CDMA systems is with only two antennas and adopts short length irregular LDPC codec, each user's data has been divided two LDPC encoded substreams being sent to two transmitter antennas at base station. Since the LDPC encoded substreams of reaching the mobile user are orthogonal to each other in space and time, the CDMA system performances (BER and SINR) can be improved much, but the multipath may ruin the orthogonalilty. To solve the problems, the paper provides the algorithms of main function modules of transmitter and receivers, gives a simple method to test the girth of LDPC codes, and analyzes the performance of MIMO-LDPC CDMA systems theoretically and experimentally. The simulation results show that the hybrid CDMA systems can have better performance than the conventional CDMA systems based on single transmitted antenna at a base station.

Girth conditioning for construction of short block length irregular LDPC codes

A girth conditioning scheme for construction of short block length low-density parity-check (LDPC) codes is presented. The parity-check matrix is generated in a column-by-column fashion under the condition that a newly added column is chosen, among a number of trial columns, to maximise the average girth of variable nodes. The girth-conditioned LDPC codes are found to give a large performance gain especially at high SNRs.