Leaky Integrate-and-fire Neuron Research Articles

Mott memristor based stochastic neurons for probabilistic computing

Many studies suggest that probabilistic spiking in biological neural systems is beneficial as it aids learning and provides Bayesian inference-like dynamics. If appropriately utilised, noise and stochasticity in nanoscale devices can benefit neuromorphic systems. In this paper, we build a stochastic leaky integrate and fire (LIF) neuron, utilising a Mott memristor’s inherent stochastic switching dynamics. We demonstrate that the developed LIF neuron is capable of biological neural dynamics. We leverage these characteristics of the proposed LIF neuron by integrating it into a population-coded spiking neural network and a spiking restricted Boltzmann machine (sRBM), thereby showcasing its ability to implement probabilistic learning and inference. The sRBM achieves a software-comparable accuracy of 87.13%. Unlike CMOS-based probabilistic neurons, our design does not require any external noise sources. The designed neurons are highly energy efficient and ultra-compact, requiring only three components: a resistor, a capacitor and a memristor device.

The Combined Effect of Spin-Transfer Torque and Voltage-Controlled Strain Gradient on Magnetic Domain-Wall Dynamics: Toward Tunable Spintronic Neuron

Magnetic domain wall (DW), as one of the promising information carriers in spintronic devices, have been widely investigated owing to its nonlinear dynamics and tunable properties. Here, we theoretically and numerically demonstrate the DW dynamics driven by the synergistic interaction between current-induced spin-transfer torque (STT) and voltage-controlled strain gradient (VCSG) in multiferroic heterostructures. Through electromechanical and micromagnetic simulations, we show that a desirable strain gradient can be created and it further modulates the equilibrium position and velocity of the current-driven DW motion. Meanwhile, an analytical Thiele’s model is developed to describe the steady motion of DW and the analytical results are quite consistent with the simulation data. Finally, we find that this combination effect can be leveraged to design DW-based biological neurons where the synergistic interaction between STT and VCSG-driven DW motion as integrating and leaking motivates mimicking leaky-integrate-and-fire (LIF) and self-reset function. Importantly, the firing response of the LIF neuron can be efficiently modulated, facilitating the exploration of tunable activation function generators, which can further help improve the computational capability of the neuromorphic system.

Leaky-integrate-fire neuron based on vertically extended drain Si[formula omitted]Ge[formula omitted] source TFET: Ultra-energy-efficient and high speed design

This article investigates the performance of a vertically extended drain double gate Si1−x Gex source tunnel field effect transistor (VD-DG-Si1−x Gex S-TFET) as a leaky integrate-and-fire (LIF) neuron. The proposed VD-DG-Si1−x Gex S-TFET structure has been designed and optimized by deploying the commercially available Silvaco TCAD. The LIF neuron using VD-DG-Si1−x Gex S-TFET requires a low spiking threshold voltage (i.e. 0.20 V) which is 5x, 3x, 5x, 1.3x, 1.55x, 7.5x, and 1.44x times less in comparison to MOSFET, Bulk FinFET, phase change device, SOI MOSFET, DG-JLFET, silicon nanowire, and DL-TFET silicon neuron. The proposed device based neuron demonstrates the least spiking energy (177 ZJ) reported to date which is 18192 times less as compared to BTBT based PDSOI MOSFET neuron. The threshold value of current is achieved at 0.20 V drain voltage which is 15x, 14x, 10x, and 1.5x less as compared to FinFET, PD-SOI MOSFET, LBIMOS, and DL-TFET, respectively. Moreover, the effects of gate metal work function, germanium mole fraction, and temperature on the spike current variations have also been investigated. Here, impact ionization is a key method for generating a neuron spike due to holes accumulated in the potential well of VD-DG-Si1−xGex S-TFET. In addition, a LIF neuron based on VD-DG-Si0.5Ge0.5 S-TFET device exhibits a 9 THz spiking frequency which is approximately 12 times higher than real nerves present in the human body. This work shows a remarkable reduction in the power consumption and the proposed device neuron is a potential start-up solution for a large scale spiking neural networks (SNN) implementation because of its better performance and compact circuitry.

Synaptic Characteristics of Fully Depleted Silicon‐on‐Insulator Metal‐Oxide‐Semiconductor Field‐Effect Transistors and Synapse‐Neuron Arrayed Neuromorphic Hardware System

A fully depleted silicon‐on‐insulator (FDSOI) metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) device is investigated as for an electronic synapse emulating the synaptic functions of the human brain with stable characteristics. Gate‐last processed FDSOI MOSFET with a high‐k/metal gate stack features a memory window of 103. Synaptic conductance is stably regulated by utilizing the FDSOI MOSFET, which offers the advantage of mitigating leakage current when compared to bulk Si MOSFET. Short‐ and long‐term plasticity are investigated by applying engineered pulse, verifying the long‐term synaptic properties of pattern recognition processes. With controllable synaptic conductance, the trade‐off between conductance change and linearity regarding the recognition rate is evaluated, attaining a recognition rate of 0.83. To verify the pre‐ and post‐synaptic weights within a real hardware‐based neuromorphic system, 5 × 6 FDSOI field‐effect transistor (FET) synapse array is interconnected to 10 × 10 leaky integrate‐and‐fire (LIF) neuron array. The synaptic plasticity of FDSOI MOSFET in post‐neurons following neuron firing in the neuron device is successfully demonstrated. These results indicate that FDSOI MOSFET devices could be applicable as synapse devices due to controllability and capability to realize signal transmissions and self‐learning processes simultaneously and used to mimic a synapse neuron network system by configuring a hardware system interconnected with the LIF neuron.

Leaky Integrate‐and‐Fire Neuron Based on Organic Electrochemical Transistor for Spiking Neural Networks with Temporal‐Coding

AbstractSpiking neural networks (SNNs) employ discrete spikes that mimic the firing of neurons in biological systems to process and transmit information. This characteristic enables SNNs to effectively capture temporal dynamics and capitalize on the time information inherent in time‐varying inputs, such as motion, audio/video streams, and other sequential data. Currently, most hardware implementations of SNNs are designed to use rate‐coding, where information is encoded in the rate of spikes. However, it still remains challenging for the hardware implementation of temporal coding in SNNs, which allows for higher input sparsity and exploits additional dimensions such as precise spike timing and relative spike timings. This study presents hardware implementations of SNNs constructed by organic electrochemical transistors (OECTs), processing temporal‐coded information. The protic dynamics in response to electrical stimuli enable the emulation of temporal integration, reset, and leaking of membrane potential in a simple leaky integrate‐and‐fire (LIF) neuron circuit. By utilizing these features, the emulated LIF neuron can be employed to construct SNNs capable of processing temporal‐coded information in complex tasks including coincidence detection and dynamic handwriting recognition, exhibiting high performance and good tolerance even when dealing with noisy datasets.

Design of spiking neural network architecture based on dendritic computation principles

The paper presents the hardware architecture design of a spiking neural network (SNN) based on dendritic computation principles. The integration of active dendritic properties into the neuronal structure of SNN aims to minimize the number of functional blocks required for hardware implementation, including synaptic connections and neurons. The available memory on the neuromorphic architecture imposes limitations on implementation, hence the need to reduce the number of functional blocks. As a test task for the SNN based on dendritic computations, we selected the image classification of eight symbols, consisting of digits one through eight. These symbols are depicted as 3×7 pixel, 1-bit images. Active dendritic properties were analyzed using the “delay plasticity” [1] principle, which introduces the mechanism of adjusting input signal delays in spiking neuron inputs. We designed an SNN model with complementary delay inputs, referred to as the active dendrite SNN, as a principle implementation. Input spikes arriving at the primary inputs are duplicated to the delay inputs after a modifiable time delay. For convenience, each delay input was set at a single value. The input images were scanned sequentially. The neural network received three direct and three inverse inputs from the six main inputs that were coded with spikes corresponding to three pixels of a string. An “on” pixel was coded with a spike arriving at a direct input, while an “off” pixel was coded with a spike arriving at the corresponding inverse input. The line scanning time was 10 μs, input width was 1 μs, and delay time was 5 μs. The optimization of spiking neuron parameters was performed through a stochastic search algorithm based on simulated annealing. The parameters optimized for the Leaky-Integrate-and-Fire (LIF) neurons included the leakage time constant (22.8 μs), firing threshold (1150 arbitrary units), and refractory period (1 μs). The active dendrite SNN training employed the tempotron learning rule [2]. The training optimized the following parameters: the maximum change in synaptic weight on potentiation and depression (0.7 and –3 arbitrary units, respectively) and the synaptic weight’s upper bound (195 arbitrary units). Complementary delayed inputs facilitated the learning of the order in which input patterns arrived for SNN neurons during training. The paper compares an SNN architecture based on dendritic computations to our previously designed two-layer SNN with a hidden perceptron layer and an output layer consisting of LIF neurons [3]. Using the same LIF neuron design, input image coding, and LIF neuron layer structure as in the proposed architecture, our two-layer SNN with a hidden perceptron layer and output layer of LIF neurons successfully recognized 3×5 images of three symbols with only 10 neurons and 63 synapses. Alternatively, the active dendrite SNN was able to recognize 3×7 images of eight symbols with four neurons and 48 synaptic weights. In conclusion, incorporating active dendrite properties into the SNN architecture for image recognition resulted in optimized functional block usage, lowering the number of neurons and synapses used by 60 and 24%, respectively.

Coincidence detection and integration behavior in spiking neural networks

AbstractRecently, the interest in spiking neural networks (SNNs) remarkably increased, as up to now some key advances of biological neural networks are still out of reach. Thus, the energy efficiency and the ability to dynamically react and adapt to input stimuli as observed in biological neurons is still difficult to achieve. One neuron model commonly used in SNNs is the leaky-integrate-and-fire (LIF) neuron. LIF neurons already show interesting dynamics and can be run in two operation modes: coincidence detectors for low and integrators for high membrane decay times, respectively. However, the emergence of these modes in SNNs and the consequence on network performance and information processing ability is still elusive. In this study, we examine the effect of different decay times in SNNs trained with a surrogate-gradient-based approach. We propose two measures that allow to determine the operation mode of LIF neurons: the number of contributing input spikes and the effective integration interval. We show that coincidence detection is characterized by a low number of input spikes as well as short integration intervals, whereas integration behavior is related to many input spikes over long integration intervals. We find the two measures to linearly correlate via a correlation factor that depends on the decay time. Thus, the correlation factor as function of the decay time shows a powerlaw behavior, which could be an intrinsic property of LIF networks. We argue that our work could be a starting point to further explore the operation modes in SNNs to boost efficiency and biological plausibility.

Emulation of neuro-mimetic dynamics via GaSb/Si heterojunction V-DGTFET leaky-integrate-fire silicon neuron

A leaky integrate and fire (LIF) neuron property is emulated using vertically developed double gate GaSb/Si tunnel field effect transistor (V-DGTFET). The suggested device can precisely replicate the neuronal dynamics after considering and proper validating the numerical simulations. Silvaco-TCAD tool is exploited for emulation of neuronal attributes and found in good agreement with earlier published research data. The article reports the membrane threshold voltage of 0.47 V which is 3.2x, 2.13x, 2.13x, 1.28x times less as compared to silicon nanowire, MOSFET, phase change device and Bulk FinFET neuron. The energy required for mimicking the neurons is computed as 0.748 aJ which is 1.2 × 109, 4 × 107, 4.68 × 107, 1.34 × 107, 7.59 × 106, 8.42 × 103, 4.30 × 103 3.34 × 105, 2.41 × 105, 1.52 × 106, 26.7,2, 3.88 × 103 times less compared to CMOS, phase change device, SOI CMOS, PCMO RRAM, SiNPN, Bulk FinFET, BTBT based PDSOI MOS, FBFET, LBIMOS, DGJLFET, Si NIPIN, DL-TFET, silicon nano wire respectively. The biasing at second gate is used to induce potential well at channel region to accumulate hole carriers produced due to impact ionization. The threshold current is achieved at 0.20 V drain voltage which is 15x, 14x, 10x, and 1.5x less as compared to FinFET, PD-SOI MOSFET, LBIMOS, and DLTFET respectively. Furthermore, calculated spiking frequency of V-DGTFET LIF neuron is 534 GHz. Thus, remarkable enhancement in frequency of operation and an ultra-low energy per spike makes this neuron device a potential solution for implementing the neuro-mimetic behaviour at large scale.

Human-Level Control Through Directly Trained Deep Spiking Q -Networks.

As the third-generation neural networks, spiking neural networks (SNNs) have great potential on neuromorphic hardware because of their high energy efficiency. However, deep spiking reinforcement learning (DSRL), that is, the reinforcement learning (RL) based on SNNs, is still in its preliminary stage due to the binary output and the nondifferentiable property of the spiking function. To address these issues, we propose a deep spiking Q -network (DSQN) in this article. Specifically, we propose a directly trained DSRL architecture based on the leaky integrate-and-fire (LIF) neurons and deep Q -network (DQN). Then, we adapt a direct spiking learning algorithm for the DSQN. We further demonstrate the advantages of using LIF neurons in DSQN theoretically. Comprehensive experiments have been conducted on 17 top-performing Atari games to compare our method with the state-of-the-art conversion method. The experimental results demonstrate the superiority of our method in terms of performance, stability, generalization and energy efficiency. To the best of our knowledge, our work is the first one to achieve state-of-the-art performance on multiple Atari games with the directly trained SNN.

A Single Schottky Barrier MOSFET-Based Leaky Integrate and Fire Neuron for Neuromorphic Computing

In this paper, a Schottky Barrier MOSFET (SB-MOSFET) based on Impact Ionization mechanism is used to design a leaky integrate and fire (LIF) neuron with considerable enhancement in area, energy and cost is proposed. Using 2D calibrated simulation, we confirmed that SB-MOSFET LIF is able to replicate the neuron behavior precisely without using external circuitry. The proposed LIF neuron shows significantly lower energy per spike of 4 pJ/spike, which is lowest among the single transistor based neurons present in the literature. The recognition precision of 89.2% has been accomplished for Modified National Institute of Standards and Technology (MNIST) image. Besides this, SB-MOSFET doesn’t require any doped regions, therefore it can be fabricated with low thermal budget.

55 nm CMOS Mixed-Signal Neuromorphic Circuits for Constructing Energy-Efficient Reconfigurable SNNs

The development of brain-inspired spiking neural networks (SNNs) has great potential for neuromorphic edge computing applications, while challenges remain in optimizing power-efficiency and silicon utilization. Neurons, synapses and spike-based learning algorithms form the fundamental information processing mechanism of SNNs. In an effort to achieve compact and biologically plausible SNNs while restricting power consumption, we propose a set of new neuromorphic building circuits, including an analog Leaky Integrate-and-Fire (LIF) neuron circuit, configurable synapse circuits and Spike Driven Synaptic Plasticity (SDSP) learning algorithm circuits. Specifically, we explore methods to minimize large leakage current and device mismatch effects, and optimize the design of these neuromorphic circuits to enable low-power operation. A reconfigurable mixed-signal SNN is proposed based on the building circuits, allowing flexible configuration of synapse weights and attributes, resulting in enhanced SNN functionality and reduced unnecessary power consumption. This SNN chip is fabricated using 55 nm CMOS technology, and test results indicate that the proposed circuits have the ability to closely mimic the behaviors of LIF neurons, synapses and SDSP mechanisms. By configuring synaptic arrays, we established varied connections between neurons in the SNN and demonstrated that this SNN chip can implement Pavlov’s dog associative learning and binary classification tasks, while dissipating less energy per spike of the order of Pico Joules per spike at a firing rate ranging from 30 Hz to 1 kHz. The proposed circuits can be used as building blocks for constructing large-scale SNNs in neuromorphic processors.

BP-SRM: A directly training algorithm for spiking neural network constructed by spike response model

Spiking neural networks (SNNs) have attracted widespread attention due to their unique bio-interpretability and low-power properties, but the non-differentiability of discrete spike sequences fired by spiking neurons brings difficulties to the learning of SNNs. Recently, surrogate gradient (SG) and back-propagation through time (BPTT) have provided an excellent idea for training SNNs constructed by leaky integrate-and-fire (LIF) neuron models. The LIF neuron model has been widely used in previous SNNs due to its simplicity and low computational cost, however, this also limits its simulation of biological neuron dynamics, reducing the biological interpretability of SNNs. In this paper, we generalize SG and BPTT to SNNs constructed by spike response model (SRM) and propose the BP-SRM algorithm. Specifically, we address why BPTT succeeded in LIF neurons-based SNNs but failed in SRM neurons-based SNNs in previous researches. Then we establish an iterative form of the SRM neuron model by selecting different state variables. Based on iterable SRM, we get the spatiotemporal dependencies between the state variables of SRM neurons-based SNNs, which allows us to derive the gradient and update weights in SNN by BP-SRM. Then we design temporal channel normalization for BP-SRM and verify the performance of the SNNs on static image dataset, dynamic image dataset and engineering dataset, including Fashion-MNIST, Weather Dataset, N-MNIST, American Sign Language Dataset and bearing fault diagnosis dataset. The experiment results indicate that BP-SRM achieves the state-of-the-art performance of SNNs.

Implementing Tensor-Organized Memory for Message Retrieval Purposes in Neuromorphic Chips

This paper introduces Tensor-Organized Memory (TOM), a novel neuromorphic architecture inspired by the human brain’s structural and functional principles. Utilizing spike-timing-dependent plasticity (STDP) and Hebbian rules, TOM exhibits cognitive behaviors similar to the human brain. Compared to conventional architectures using a simplified leaky integrate-and-fire (LIF) neuron model, TOM showcases robust performance, even in noisy conditions. TOM’s adaptability and unique organizational structure, rooted in the Columnar-Organized Memory (COM) framework, position it as a transformative digital memory processing solution. Innovative neural architecture, advanced recognition mechanisms, and integration of synaptic plasticity rules enhance TOM’s cognitive capabilities. We have compared the TOM architecture with a conventional floating-point architecture, using a simplified LIF neuron model. We also implemented tests with varying noise levels and partially erased messages to evaluate its robustness. Despite the slight degradation in performance with noisy messages beyond 30%, the TOM architecture exhibited appreciable performance under less-than-ideal conditions. This exploration into the TOM architecture reveals its potential as a framework for future neuromorphic systems. This study lays the groundwork for future applications in implementing neuromorphic chips for high-performance intelligent edge devices, thereby revolutionizing industries and enhancing user experiences within the power of artificial intelligence.

Sharing leaky-integrate-and-fire neurons for memory-efficient spiking neural networks.

Spiking Neural Networks (SNNs) have gained increasing attention as energy-efficient neural networks owing to their binary and asynchronous computation. However, their non-linear activation, that is Leaky-Integrate-and-Fire (LIF) neuron, requires additional memory to store a membrane voltage to capture the temporal dynamics of spikes. Although the required memory cost for LIF neurons significantly increases as the input dimension goes larger, a technique to reduce memory for LIF neurons has not been explored so far. To address this, we propose a simple and effective solution, EfficientLIF-Net, which shares the LIF neurons across different layers and channels. Our EfficientLIF-Net achieves comparable accuracy with the standard SNNs while bringing up to ~4.3× forward memory efficiency and ~21.9× backward memory efficiency for LIF neurons. We conduct experiments on various datasets including CIFAR10, CIFAR100, TinyImageNet, ImageNet-100, and N-Caltech101. Furthermore, we show that our approach also offers advantages on Human Activity Recognition (HAR) datasets, which heavily rely on temporal information. The code has been released at https://github.com/Intelligent-Computing-Lab-Yale/EfficientLIF-Net.

A tunable leaky integrate-and-fire neuron based on one neuromorphic transistor and one memristor

Artificial leaky integrate-and-fire (LIF) neurons have attracted significant attention for building brain-like computing and neuromorphic systems. However, previous artificial LIF neurons have primarily focused on implementing integrate-and-fire function, and the function of dendritic modulation has rarely been reported. In this Letter, a tunable artificial LIF neuron based on an IGZO electric-double-layer (EDL) transistor and a TaOx memristor is fabricated, and dendritic modulation is investigated. An IGZO-based EDL transistor with a modulatory terminal is used to realize dendritic nonlinear integration and filtering capability, as well as the tunable neural excitability. An Ag/TaOx/ITO threshold switching memristor mimics the all-or-nothing spiking and threshold switching of the soma. By incorporating these two components in a customized way, such artificial LIF neuron can emulate the key function of biological neuron with rich computational flexibility. Our artificial LIF neurons with rich nonlinear dynamics have great potential to perform more complex tasks in future spiking neuromorphic systems.

Feasibility study on the application of a spiking neural network in myoelectric control systems.

In recent years, the effectiveness of a spiking neural network (SNN) for Electromyography (EMG) pattern recognition has been validated, but there is a lack of comprehensive consideration of the problems of heavy training burden, poor robustness, and high energy consumption in the application of actual myoelectric control systems. In order to explore the feasibility of the application of SNN in actual myoelectric control systems, this paper investigated an EMG pattern recognition scheme based on SNN. To alleviate the differences in EMG distribution caused by electrode shifts and individual differences, the adaptive threshold encoding was applied to gesture sample encoding. To improve the feature extraction ability of SNN, the leaky-integrate-and-fire (LIF) neuron that combines voltage-current effect was adopted as a spike neuron model. To balance recognition accuracy and power consumption, experiments were designed to determine encoding parameter and LIF neuron release threshold. By conducting the gesture recognition experiments considering different training test ratios, electrode shifts, and user independences on the nine-gesture high-density and low-density EMG datasets respectively, the advantages of the proposed SNN-based scheme have been verified. Compared with a Convolutional Neural Network (CNN), Long Short-Term Memory Network (LSTM) and Linear Discriminant Analysis (LDA), SNN can effectively reduce the number of repetitions in the training set, and its power consumption was reduced by 1-2 orders of magnitude. For the high-density and low-density EMG datasets, SNN improved the overall average accuracies by about (0.99 ~ 14.91%) under different training test ratios. For the high-density EMG dataset, the accuracy of SNN was improved by (0.94 ~ 13.76%) under electrode-shift condition and (3.81 ~ 18.95%) in user-independent case. The advantages of SNN in alleviating the user training burden, reducing power consumption, and improving robustness are of great significance for the implementation of user-friendly low-power myoelectric control systems.

Python-Based Circuit Design for Fundamental Building Blocks of Spiking Neural Network

Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the X variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips.

A Super-Efficient TinyML Processor for the Edge Metaverse

Although the Metaverse is becoming a popular technology in many aspects of our lives, there are some drawbacks to its implementation on clouds, including long latency, security concerns, and centralized infrastructures. Therefore, designing scalable Metaverse platforms on the edge layer can be a practical solution. Nevertheless, the realization of these edge-powered Metaverse ecosystems without high-performance intelligent edge devices is almost impossible. Neuromorphic engineering, which employs brain-inspired cognitive architectures to implement neuromorphic chips and Tiny Machine Learning (TinyML) technologies, can be an effective tool to enhance edge devices in such emerging ecosystems. Thus, a super-efficient TinyML processor to use in the edge-enabled Metaverse platforms has been designed and evaluated in this research. This processor includes a Winner-Take-All (WTA) circuit that was implemented via a simplified Leaky Integrate and Fire (LIF) neuron on an FPGA. The WTA architecture is a computational principle in a neuromorphic system inspired by the mini-column structure in the human brain. The resource consumption of the WTA architecture is reduced by employing our simplified LIF neuron, making it suitable for the proposed edge devices. The results have indicated that the proposed neuron improves the response speed to almost 39% and reduces resource consumption by 50% compared to recent works. Using our simplified neuron, up to 4200 neurons can be deployed on VIRTEX 6 devices. The maximum operating frequency of the proposed neuron and our spiking WTA is 576.319 MHz and 514.095 MHz, respectively.

Neuronal Dynamics: from Complexity to Simplicity

An analytical study is performed to obtain the phase description of a network of Leaky Integrate-and-Fire (LIF) neurons. We start by discussing the behaviour of single LIF neuron in the presence of a constant current and then derive the corresponding phase oscillator model for some parameters setup. In the case of two identical LIF neurons where the interactions are ruled by the weak pulse input, we determine the analytical expression for the phase response curve. Next, we extend the phase reduction principles to a generic case of N networks of identical LIF neurons. The final model of so-called phase oscillators is widely used to study synchronization in many natural systems. Through numerical simulations, we find an agreement between the LIF neurons and the phase oscillators model.

Artificial LIF Neuron With Bursting Behavior Based on Threshold Switching Device

Bio-inspired computing architecture based on artificial neurons and synapses is attracting intensive attention in the field of power-efficient artificial intelligence. Artificial neurons with bio-inspired firing patterns can significantly improve the computing power of neural networks. However, the reported neuron circuits with burst firing lack the changing of interspike interval (ISI) under different amplitudes of input pulses. Here, a compact leaky integrate-and-fire (LIF) neuron circuit based on the Ag/Ti/HfSe2-xOy/Pt threshold switching (TS) device with a feedback module is designed to achieve bio-inspired burst firing. By adjusting the oxidation conditions and embedding an ultrathin Ti layer, the stability, switching speed, and power consumption of the device have been significantly improved, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {hold}}$ </tex-math></inline-formula> have been reduced. These improvements are attributed to the synergistic effect of diffusion barrier and point contact caused by the naturally formed uneven TiOx layer at the interface through the embedding Ti layer. Taking advantage of the low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {hold}}$ </tex-math></inline-formula> value of the Ag/Ti/HfSe2-xOy/Pt device, the bionic bursting functions have been realized in the LIF neuron, and the spiking regularity of the burst firing can be modulated through the adjustment of the input pulse.