Leakage Power Estimation Research Articles

Low‐complexity GNSS carrier leakage detection and estimation via abnormal direct current energy identification

Carrier leakage due to faults within the satellite payload results in a waste of transmit power and affects the receiver functions. The existing methods are generally performed in the transform domain with high computation load and are unable to estimate the carrier leakage power. This letter presents a low-complexity algorithm by monitoring the abnormal direct current component of baseband signal. The quantitative relationship between carrier leakage power and test statistics is derived here, and the capability of carrier leakage power estimation is provided. Analytical and simulation results show that it achieves a detection rate of more than 99% for carrier-to-noise ratio larger than 42 dB-Hz and coherent integration time larger than 10 ms. It also greatly saves millions of multiplications compared with the conventional frequency-domain method.

Compact Transient Thermal Model of Microfluidically Cooled Three-Dimensional Stacked Chips With Pin-Fin Enhanced Microgap

Abstract Three-dimensional (3D) stacked integrated circuit (SIC) chips are one of the most promising technologies to achieve compact, high-performance, and energy-efficient architectures. However, they face a heat dissipation bottleneck due to the increased volumetric heat generation and reduced surface area. Previous work demonstrated that pin-fin enhanced microgap cooling, which provides fluidic cooling between layers could potentially address the heat dissipation challenge. In this paper, a compact multitier pin-fin single-phase liquid cooling model has been established for both steady-state and transient conditions. The model considers heat transfer between layers via pin-fins, as well as the convective heat removal in each tier. Spatially and temporally varying heat flux distribution, or power map, in each tier can be modeled. The cooling fluid can have different pumping power and directions for each tier. The model predictions are compared with detailed simulations using computational fluid dynamics/heat transfer (CFD/HT). The compact model is found to run 120–600 times faster than the CFD/HT model, while providing acceptable accuracy. Actual leakage power estimation is performed in this codesign model, which is an important contribution for codesign of 3D-SICs. For the simulated cases, temperatures could decrease 3% when leakage power estimation is adopted. This model could be used as electrical-thermal codesign tool to optimize thermal management and reduce leakage power.

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

As the development of deep-submicron and nano-technology, leakage power minimisation becomes as important as dynamic power reduction in IC design. In order to achieve low-power state assignment for finite-state machine (FSM) synthesis, a multi-population genetic algorithm (MPGA)-based state assignment method is proposed. MPGA consists of an outer-loop and a set of inner-GAs. In MPGA, inner-GA is a local search component for finding low-power state assignment. Selection, crossover and mutation are used to perform variations on individuals. Cost function is defined based on power dissipation formulation of complementary metal oxide semiconductor (CMOS) gate for dynamic power and leakage power estimation. The outer-loop is used to optimise the parameters of inner-genetic algorithm (GA) through population variation schema, intra-specific competition and newborn. Twenty-three FSMs that were commonly used as benchmarks are employed to test the effectiveness of MPGA and compare different state assignment methods. Experimental results show MPGA achieves a significant improvement over the previous publications both on dynamic power and leakage power reduction in most benchmarks.

Leakage Analysis and Solution of the RFID Analog Front-END

The identification and modeling of different leakage components are very important for estimation and reduction of leakage power, especially low-power applications, such as RFID chip. This paper proposes a theory about leakage mechanism of RFID chip and proves the theory. The one contribution of the paper is the proposed theory about leakage mechanism of RFID chip. The other contribution is that it proves the differences between tape-out verification results and computer simulation results and that to what degree the differences occur for different circuits. And when the source potential is much lower than the substrate potential, tape-out verification results and computer simulation results have larger differences. The test results show that the actual leakage power increases 26.3 times compares with the computer simulation results’ when the source potential is -750mV.

Leak-Gauge: A late-mode variability-aware leakage power estimation framework

Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical process parameters, threshold voltage and effective channel length. Our subthreshold leakage current model is shown to fit closely on the HSPICE Monte Carlo simulation data with an average coefficient of determination (R2) value of 0.9984 for all the cells of a standard library. We demonstrate the adjustability of this model to wider ranges of variation and its extendability to future technology scalings. We also present a complete framework for estimation of full-chip leakage power and show that our framework which we call Leak-Gauge, imposes little timing penalty on the system design flow and is applicable to real design cases.

Dynamic and Leakage Power Estimation in Register Files Using Neural Networks

Efficient power consumption and energy dissipation in embedded devices and modern processors is becoming increasingly critical due to the limited energy supply available from the current battery technologies. It is vital for chip architects, circuit, and processor designers to evaluate the energy per access, the power consumption and power leakage in register files at an early stage of the design process in order to explore power/performance tradeoffs, and be able to adopt power efficient architectures and layouts. Power models and tools that would allow architects and designers the early prediction of power consumption in register files are vital to the design of energy-efficient systems. This paper presents a Radial Base Function (RBF) Artificial Neural Network (ANN) model for the prediction of energy/access and leakage power in standard cell register files designed using optimized Synopsys Design Ware components and an UMC 130 nm library. The ANN model predictions were compared against experimental results (obtained using detailed simulation) and a nonlinear regression-based model, and it is observed that the ANN model is very accurate and outperformed the nonlinear model in several statistical parameters. Using the trained ANN model, a parametric study was carried out to study the effect of the number of words in the file (D), the number of bit in one word (W) and the total number of Read and Write Ports (P) on the values of energy/access and the leakage power in standard cell register files.

Temperature-Aware Leakage Estimation Using Piecewise Linear Power Models

Due to the superlinear dependence of leakage power consumption on temperature, and spatial variations in on-chip thermal profiles, methods of leakage power estimation that are known to be accurate require detailed knowledge of thermal profiles. Leakage power depends on the integrated circuit (IC) thermal profile and circuit design style. Here, we show that piecewise linear models can be used to permit accurate leakage estimation over the operating temperature ranges of the ICs. We then show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have a similar impact on the average temperature of the layer. These two observations support the proof that, for wide ranges of design styles and operating temperatures, extremely fast, coarse-grained thermal models, combined with piecewise linear leakage power consumption models, enable the estimation of chip-wide leakage power consumption. These results are further confirmed through comparisons with leakage estimates based on detailed, time-consuming thermal analysis techniques. Experimental results indicate that, when compared with a leakage analysis technique that relies on accurate spatial temperature estimation, the proposed technique yields a 59,259× to 1,790,000× speedup in estimating leakage power consumption, while maintaining accuracy.

Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits

In this paper, we propose a methodology to solve leakage power self-consistently with temperature to predict thermal runaway. We target 28-nm-technology-node FinFET-based circuits as they are more prone to thermal runaway because of self-heating and less efficient heat dissipation compared to bulk metal-oxide-semiconductor field-effect transistors. We have generated thermal models for logic cells-inverter, NAND, and NOR-to self-consistently determine the temperature map of a circuit block. Our cell-level thermal models account for lateral heat flow (contribution of neighboring cells) along with vertical heat dissipation to the heat sink. We predict positive feedback between subthreshold leakage and temperature for all the cells in a given floor plan. Our proposed condition for thermal runaway shows the design tradeoff between the primary input (PI) activity of a circuit block, subthreshold leakage at the room temperature, and thermal resistance of the package. We show that, in FinFET circuits, thermal runaway can occur at the International Technology Roadmap for Semiconductors-specified subthreshold leakage (of 150 for high performance) for a nominal PI activity of 0.5 and typical package thermal resistance. In addition, we show that the maximum temperature rise in an integrated circuit is limited by package limitations.

Efficient Statistical Leakage Power Analysis Method for Function Blocks Considering All Process Variations

With technology scaling into nanometer regime, rampant process variations impact visible influences on leakage power estimation of very large scale integrations (VLSIs). In order to deal with the case of large inter- and intra-die variations, we induce a novel theory prototype of the statistical leakage power analysis (SLPA) for function blocks. Because inter-die variations can be pinned down into a small range but the number of gates in function blocks is large(>1000), we continue to simplify the prototype. At last, we induce the efficient methodology of SLPA. The method can save much running time for SLPA in the low power design since it is of the local-updating advantage. A large number of experimental data show that the method only takes feasible running time (0.32 s) to obtain accurate results (3 σ -error <0.5% on maximum) as function block circuits simultaneous suffer from 7.5%(3 σ/mean) inter-die and 7.5% intra-die length variations, which demonstrates that our method is suitable for statistical leakage power analysis of VLSIs under rampant process variations.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

LEAKAGE CURRENT IN DEEP-SUBMICRON CMOS CIRCUITS

The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power applications. This paper explores the various transistor intrinsic leakage mechanisms including the weak inversion, the drain-induced barrier lowering, the gate-induced drain leakage, and the gate oxide tunneling.