LEAKAGE CURRENT IN DEEP-SUBMICRON CMOS CIRCUITS

Abstract

The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power applications. This paper explores the various transistor intrinsic leakage mechanisms including the weak inversion, the drain-induced barrier lowering, the gate-induced drain leakage, and the gate oxide tunneling.