Leakage Current Research Articles

A Zero-Voltage-Transition H5-Type Transformerless Photovoltaic Grid-Connected Inverter

Efficiency and leakage current are two major issues for transformerless grid-connected inverters (TLI). Soft-switching technologies can reduce switching losses and be applied in TLIs. Herein, a zero-voltage-transition H5 type (ZVT-H5) inverter with soft turn-on and turn-off transitions of high-frequency main switches is derived from basic resonant tanks. Compared with the hard-switching H5 (HS-H5) inverter, the conversion efficiency of ZVT-H5 is significantly improved. Moreover, the reverse recovery problem of freewheeling diodes is alleviated under the operation of the auxiliary resonant network. Meanwhile, a diode clamping branch is employed to achieve constant common-mode characteristic for the ZVT-H5. The construction process of the proposed topology is described, and the operation principle of the auxiliary resonant network is analyzed. Moreover, the resonant parameter design of ZVT-H5 and its circuit performance are discussed in detail. Finally, the experimental results of a 3-kW prototype at 100 kHz switching frequency are provided to verify the effectiveness of the ZVT-H5.

Development of a model for diagnosing rotor conditions in the parallel connection of synchronous generators with the network

This article introduces a model for diagnosing rotor angular changes in generators when integrating synchronous generators into the grid. The model addresses issues like leakage currents, reverse moments, and stator bushing short circuits caused by rotor angle changes during parallel addition of large-capacity synchronous generators. Its unique approach simplifies precise synchronization during parallel connection and enables continuous graphical monitoring of rotor angle changes through computer programs. Experimental results from 110 MW synchronous generators at "Navoi Thermal Power Plant" JSC validate the model's effectiveness. It is designed to resolve rotor angle change challenges when integrating synchronous generators of varying capacities into existing power plants, ensuring uninterrupted electricity supply and optimizing technical and economic performance. The model aims to enhance operational efficiency and reduce costs for electricity consumers.

Design and Implementation of Transformer-less Common-Ground Inverter With Reduced Components

Nowadays, common-ground-type (CGT) based transformer-less inverters (TIs) are gaining more popularity in photovoltaic (PV) applications owing to their low cost, weight of the systems, losses and zero ground leakage current. For PV applications, a separate boost converter is often used to boost the low PV array voltage, resulting in increased component count, cost and lower efficiency. To resolve this issue, switched-capacitor (SC) based CGT inverter with reduced component count is proposed in this paper. The proposed amalgamation of CGT and SC technique, results in inherent boosting and zero ground leakage current. In the proposed inverter, SCs are connected in series/parallel with the dc voltage source for several instances in a fundamental cycle preserving the self-voltage balancing ability. Therefore, the proposed topology is devoid of voltage sensors to balance the voltage across SCs. Further, A simplified logic gatebased pulse-width-modulation strategy is developed. In addition, the benefits of proposed inverter are highlighted and compared with the other recent SC inverter topologies with regard to boosted voltage, elimination of leakage current and reduced component count. A laboratory prototype is developed by using DS1202/1302 dSPACE controller and experimental results are presented for both steady state and dynamic conditions and verifying the feasibility of the proposed TI.

Ferroelectric photovoltaic effect engineered by phase transition and defect neutralization in K0.5Na0.5NbO3 film

As an excellent light transmission material, K0.5Na0.5NbO3 (KNN) shows considerable potential in ferroelectric photovoltaics. However, poor leakage and non-intrinsic polarization limit their photoelectric conversion since they play important roles in the generation, separation and transport of photogenerated carriers. This work realizes the simultaneous improvement of bandgap, ferroelectric and leakage by the introduction of charged group BiFeO3 (BFO), which neutralizes the defects and reduces the leakage current of the films by about two orders of magnitude and increases the remanent polarization to 15.4 μC/cm2 due to the phase transition. Meanwhile, the addition of Fe also introduces impurity energy levels into the KNN films and reduces the bandgap. The open-circuit voltage of the 0.98KNN-0.02BFO film is increased by about 2.5 times. This work provides a feasible way to enhance the ferroelectric photovoltaic performance of KNN films and accelerate their application.

E-MLB: Multilevel Benchmark for Event-Based Camera Denoising

Event cameras, such as dynamic vision sensors (DVS), are biologically inspired vision sensors that have advanced over conventional cameras in high dynamic range, low latency and low power consumption, showing great application potential in many fields. Event cameras are more sensitive to junction leakage current and photocurrent as they output differential signals, losing the smoothing function of the integral imaging process in the RGB camera. The logarithmic conversion further amplifies noise, especially in low-contrast conditions. Recently, researchers proposed a series of datasets and evaluation metrics but limitations remain: 1) the existing datasets are small in scale and insufficient in noise diversity, which cannot reflect the authentic working environments of event cameras; and 2) the existing denoising evaluation metrics are mostly referenced evaluation metrics, relying on APS information or manual annotation. To address the above issues, we construct a large-scale event denoising dataset (multilevel benchmark for event denoising, E-MLB) for the first time, which consists of 100 scenes, each with four noise levels, that is 12 times larger than the largest existing denoising dataset. We also propose the first nonreference event denoising metric, the event structural ratio (ESR), which measures the structural intensity of given events. ESR is inspired by the contrast metric, but is independent of the number of events and projection direction. Based on the proposed benchmark and ESR, we evaluate the most representative denoising algorithms, including classic and SOTA, and provide denoising baselines under various scenes and noise levels. The corresponding results and codes are available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/KugaMaxx/cuke-emlb</uri>

A New Five-Level Switched-Capacitor-Based Transformer-less Common-Grounded Grid-Tied Inverter

This paper proposes a new switched-capacitor grid-tied inverter. The proposed topology can eliminate leakage current using a common-grounded strategy. Also, the proposed topology generates a five-level output voltage waveform using a single input dc source with a voltage boosting factor of 2. This structure uses six power switches, two diodes, and two self-balanced capacitors. The proposed inverter has some advantages such as a common-grounded feature, eliminated leakage current, and voltage boosting feature with single-stage energy conversion operation. Also, the proposed topology can support both active and reactive powers and generate a perfect sinusoidal output current injected into the grid. Also, to control both active and reactive powers an efficient control strategy is applied. To generate the precise gate pulses for the power switches, the introduced efficient control strategy is applied. Also, comprehensive discussions on the operating modes of the proposed inverter, Capacitor charging current analysis, the control technique, and design considerations are presented. To show the advantages and differences of the proposed inverter with some other recently presented switched-capacitor-based grid-tied inverters a comparison study is considered. Finally, to validate the performance and feasibility of the proposed inverter, various experimental results based on a 620 W experimental prototype are presented.

Improved electrical performance of ultra-thin BexMg1−xO films using super-cycle atomic layer deposition

BexMg1−xO ultra-thin dielectric films, deposited via super-cycle ALD and controlled sub-cycle ratio, show a POT of 3.7 nm, an EOT of 1.3 nm, and low leakage current, suitable for dynamic random access memory.

Improved power semiconductor dynamic testing circuit to suppress leakage current

Improved power semiconductor dynamic testing circuit to suppress leakage current

Ovonic threshold switching-based artificial afferent neurons for thermal in-sensor computing.

Artificial afferent neurons in the sensory nervous system inspired by biology have enormous potential for efficiently perceiving and processing environmental information. However, the previously reported artificial afferent neurons suffer from two prominent challenges: considerable power consumption and limited scalability efficiency. Herein, addressing these challenges, a bioinspired artificial thermal afferent neuron based on a N-doped SiTe ovonic threshold switching (OTS) device is presented for the first time. The engineered OTS device shows remarkable uniformity and robust endurance, ensuring the reliability and efficacy of the artificial afferent neurons. A substantially decreased leakage current of the SiTe OTS device by nitrogen doping results in ultra-low power consumption less than 0.3 nJ per spike for artificial afferent neurons. The inherent temperature response exhibited by N-doped SiTe OTS materials allows us to construct a highly compact artificial thermal afferent neuron over a wide temperature range. An edge detection task is performed to further verify its thermal perceptual computing function. Our work provides an insight into OTS-based artificial afferent neurons for electronic skin and sensory neurorobotics.

Wet chemical poly-Si(n) wrap-around removal for TOPCon solar cells

This work gives an overview on different technological solutions for polysilicon removal in industrial tunnel oxide passivated contact (i-TOPCon) n-type silicon solar cell fabrication. The removal of parasitically deposited poly-Si layers on the front and the edges is a mandatory requirement for a low reverse bias junction leakage current (Irev). A polysilicon removal study on wafer level shows (i) that the efficient removal of the surface oxide layer before poly-Si etching is crucial to achieve short etching times and (ii) that an additive in the KOH solution enhances etching selectivity between poly-Si and silicon oxide surfaces. To evaluate the impact on device level, TOPCon cells have been fabricated in parallel using in-situ n-doped PECVD and LPCVD layers, as well as ex-situ LPCVD poly-Si layers, with another variation of poly-Si removal processes, namely wet chemical inline, wet chemical batch cluster and atmospheric dry etching (ADE). Our results show that a two-minute inline polysilicon removal in hot KOH meets the Irev qualification in case of as deposited in-situ doped layers, whereas for ex-situ doped layers a batch process with a five-minute KOH etching time is needed. LPCVD poly-Si cells show efficiencies above 23%, PECVD poly-Si cells with a batch cluster poly-Si removal process up to 23.4%.

Inkjet printing high mobility indium-zinc-tin oxide thin film transistor

Metal oxide thin film transistor has been widely used in flat panel display industry because of its low leakage current, high mobility and large area uniformity. Besides with the development of printed display technology, inkjet printing process can fabricate the customizable patterns on diverse substrates without the need for vacuum or lithography, can significantly reduce cost and has received more and more attention. In this paper, we fabricate a bottom gate bottom contact structure thin film transistor (TFT) with indium-zinc-tin-oxide (IZTO) semiconductor using inkjet printing process. The surface morphology of the printed IZTO film is modified by adjusting the solvent composition and solute concentration of the printing precursor ink. The experimental result show that the use of binary solvents can effectively overcome the coffee ring shape caused by the accumulation of solute edge during the volatilization process of a single solvent, and finally show a uniform and flat contour surface. Further increase in solute concentration is in favor of formation of convex surface topology. The reason for the formation of the flat surface of the oxide film is the balance between the inward Marangoni reflux of the solute and the outward capillary flow during volatilization. In addition, using binary solvents printed IZTO thin film transistor exhibit excellent electrical properties. The ratio of width/length=50/30 exhibit a high on-off ratio of 1.21×10&lt;sup&gt;9&lt;/sup&gt;,a high saturation field-effect mobility of 16.6 cm&lt;sup&gt;2&lt;/sup&gt;·V&lt;sup&gt;-1&lt;/sup&gt;·s&lt;sup&gt;-1&lt;/sup&gt;,a low threshold voltage of 0.84 V and subthreshold swing of 0.24 V/dec. The uniform and flat active layer thin film pattern can form good contact with the source leakage electrode, and the contact resistance of TFT devices with different width-to-length ratios is less than 1000 Ω, which can achieve the basic conditions of high mobility thin film transistors prepared by inkjet printing. Therefore, using mixture solvents provides a universal and facile way to print oxide films with desired surface topology and provide a visible path for inkjet printing of high-mobility thin film transistors.

A Transformerless Photovoltaic System Employing a Cubic Cell Boost Converter for Low Voltage Application

A photovoltaic (PV) system is commonly used to satisfy the power demand of the utility. This paper investigates the utilization of a high voltage gain Cubic Cell Boost Converter (CCBC) in a transformerless photovoltaic (PV) system for low voltage applications. The proposed system is a combination of a CCBC and a three-phase inverter creating a two-stage three-phase PV system. The CCBC is linked with the low-scale PV sources to step up its input DC voltage and maintain a constant DC bus voltage by employing the Perturb and Observe (P&amp;O) Maximum Power Point Tracking (MPPT) control algorithm. The DC bus is further connected to an LCL filter based three-phase inverter using a synchronous reference frame (dq) control scheme to power the three-phase utility. The proposed combination is validated by simulating in MATLAB/ SIMULINK environment for a 5.5 kW PV source and achieved an efficiency of 91% with 1.91% of inverter Total Harmonic Distortion (THD) at unity power factor. In the proposed system, CCBC with P&amp;O MPPT control provides a high step-up DC bus voltage with less input current ripple and output voltage ripple and maintains a constant DC bus under variable solar irradiance. This work does not account for the common leakage current that is often produced in a transformerless PV system.

Improved Integrated Modulation Strategy for Dual-Parallel Three-Level Inverters to Suppress Leakage Currents

Improved Integrated Modulation Strategy for Dual-Parallel Three-Level Inverters to Suppress Leakage Currents

Flux potentials of local talc in low voltage electro-porcelain insulator production

Increasing demand for accessories like porcelain electric insulators have continued in developing countries causing overdependence on imported products. Meanwhile, raw materials for their local production are available in commercial quantities with high firing temperature being the major challenge. Hence, the need for fluxing agents that can reduce the working temperature led to the investigation of Talc as a partial replacement of conventional Feldspar. An optimum replacement of 10% Feldspar with Talc was adopted, and this recipe showed microstructurally enriched glassy phase, primary and secondary Mullite with other crystalline phases like Cristobalite, Microcline and Albite at 1200oC with micropores evident in both the Talc and Feldspar formulations. The produced insulator fired at 1200oC offered an optimum thermal conductivity of 0.2768W/mK with reductions in water absorption, apparent porosity and linear shrinkage by 78.29%, 76.02% and 19.75% respectively with a 9.48% rise in bulk density. The electrical performance comprised Inception, Withstand and Breakdown Voltages of 10.2 kV, 14 kV and 20 kV respectively at leakage currents of 0.2 mA, 1.2 mA and 2 mA accordingly. With a withstand voltage above 11 kV and breakdown voltage below 22 kV, this pin-type porcelain insulator will find wide application in both electric substations and end user load points like commercial and residential electric power lines. The novelty lies on the fluxing and filler potentials of Talc as a locally-sourced mineral in porcelain insulator production which increases the market value of Nigerian Talc while reducing importation, costs of energy and raw materials in porcelain production.

A method for suppressing leakage current of non-isolated integrated on-board EV battery charger

A method for suppressing leakage current of non-isolated integrated on-board EV battery charger

Structure, bonding and electronic characteristics of amorphous Se.

Ovonic threshold switching (OTS) selectors can effectively improve the storage density and suppress the leakage current of advanced phase-change memory devices. As a prototypical OTS material, amorphous GeSe is widely investigated. But the attention paid to amorphous Se (i.e., the functional constituent in amorphous GeSe) has been very limited up to now. Here we have explored the structure, bonding and electronic characteristics of amorphous Se using ab initio molecular dynamics simulations. The results reveal that the Se atoms in amorphous Se tend to form 2-coordinated configurations, and they connect with each other to form long chains. The fraction of the vibrational density of state located in the high frequency range is relatively large, and the formation energy of the Se-Se bond is as large as 4.44 eV, hinting that the Se-Se bonds in chains possess high stability. In addition, the mid-gap state related to the OTS behavior is also found in amorphous Se despite the small proportion. Our findings enrich the knowledge of amorphous Se, which aids the applications of Se-based OTS selectors.

Frequency-Modulated Charge Pumping: Defect Measurements With High Gate Leakage

Charge pumping is one of the most relied techniques used to quantify interface defects in metal-oxide-semiconductor devices. However, conventional charge pumping is easily hindered by excessive gate leakage currents, which render the technique unsuitable for advanced technology nodes. We demonstrate a new frequency-modulated charge pumping methodology in which we transform the quasi-dc charge pumping measurement into an ac measurement. The ac detection scheme is highly resistant to gate leakage currents and extends the usefulness of charge pumping as a defect monitoring tool for future technologies.

Preparation of high-performance large-area perovskite solar cells by atomic layer deposition of metal oxide buffer layer

Perovskite solar cells have been widely recognized as the most promising new-type photovoltaic device due to its power conversion efficiency rapidly increasing from 3.8% to over 26% in merely fifteen years. However, the high performances are achieved mainly on small area cells with an active area lower than 0.1 cm&lt;sup&gt;2&lt;/sup&gt;. When enlarging the active area of perovskite solar cells, the efficiency falls dramatically. So, how to reduce the gap between performances of small area cells and large area cells gradually becomes a critical point in the path towards the commercialization of perovskite photovoltaic technology. Herein, a strategy of pre-growing thin layer of TiO&lt;sub&gt;2&lt;/sub&gt; on a rough FTO substrate by atomic layer deposition method before spin-coating SnO&lt;sub&gt;2&lt;/sub&gt; nanoparticles is proposed. Due to the inherent conformal film growth mode of atomic layer deposition, the FTO substrate can be completely covered by TiO&lt;sub&gt;2&lt;/sub&gt;, thus preventing the direct contact between local protrusions of FTO and perovskite layer and impeding the current leakage phenomenon, which can be verified by the measurements from X-ray photoelectron spectroscopy, scanning electron microscopy, and atomic force microscopy, and further proved by the dark current measurement. By using this method, the repeatability and consistency of the small area cell fabrication technology on the same substrate are improved obviously. The improved electron transport process revealed by photoluminescence results and incident light management process revealed by external quantum efficiency results also brings about better solar cell performances. More importantly, highly efficient 0.5 cm&lt;sup&gt;2&lt;/sup&gt; large area perovskite solar cells are fabricated through optimization of TiO&lt;sub&gt;2&lt;/sub&gt; thickness. When growing 200 cycles TiO&lt;sub&gt;2&lt;/sub&gt; (~9 nm in thickness) by using atomic layer deposition technology, the champion large area perovskite solar cell possesses a power conversion efficiency as high as 24.8% (certified 24.65%). The device performances also show excellent repeatability between different fabrication batches. The perovskite solar cell with TiO&lt;sub&gt;2&lt;/sub&gt; buffer layer grown by the atomic layer deposition method can still retain over 95% of its initial efficiency after having been stored in a nitrogen atmosphere for 1500 h. The technique proposed in this paper can be helpful in manufacturing perovskite solar cell modules in the realistic photovoltaic market and can be extended to the large area fabrication of other perovskite optoelectronic devices such as light emitting diode, laser and detector.

240 nm AlGaN-based deep ultraviolet micro-LEDs: size effect versus edge effect

240 nm AlGaN-based micro-LEDs with different sizes are designed and fabricated. Then, the external quantum efficiency (EQE) and light extraction efficiency (LEE) are systematically investigated by comparing size and edge effects. Here, it is revealed that the peak optical output power increases by 81.83% with the size shrinking from 50.0 to 25.0 μm. Thereinto, the LEE increases by 26.21% and the LEE enhancement mainly comes from the sidewall light extraction. Most notably, transverse-magnetic (TM) mode light intensifies faster as the size shrinks due to the tilted mesa side-wall and Al reflector design. However, when it turns to 12.5 μm sized micro-LEDs, the output power is lower than 25.0 μm sized ones. The underlying mechanism is that even though protected by SiO2 passivation, the edge effect which leads to current leakage and Shockley-Read-Hall (SRH) recombination deteriorates rapidly with the size further shrinking. Moreover, the ratio of the p-contact area to mesa area is much lower, which deteriorates the p-type current spreading at the mesa edge. These findings show a role of thumb for the design of high efficiency micro-LEDs with wavelength below 250 nm, which will pave the way for wide applications of deep ultraviolet (DUV) micro-LEDs.

Implementation of Ripple Carry Adder and Carry Save Adder using 7nm FinFET Technology

The semiconductor industry’s continuous effort to miniaturize and be more powerful to increase the overall performance. This has led to the use of FinFET technology for packing more transistors into a smaller space and using power more efficiently compared to planner MOS technologies. Compared to the MOS technology, FinFET technology provides better advantages such as improved transistor performance, lower leakage currents, and enhanced power efficiency. The proposed work includes integrating fundamental components like the NAND gate, 2:1 MUX, and full adder (FA). These components are combined to build both Ripple Carry Adder (RCA) and Carry Save Adder (CSA). The work is carried out using 7nm FinFET technology and this research involves a thorough analysis of power consumption and propagation delay, with the implementation carried out using the Cadence Virtuoso tool. The study highlights the improved performance of 7nm FinFET technology compared to MOSFETs.