Leakage Current Values Research Articles

Influence of the gate leakage current on the noise performance of MESFETs and MODFETs

In this paper, the influence of the gate leakage current on the noise performance of MESFETs and MODFETs is investigated. Both a simple analytical model and a more realistic numerical model have been developed. It is shown that the noise performance is strongly dependent on the gate leakage current value, especially at low frequency. The theoretical results are discussed and compared with experimental ones.

Electrical properties of sol-gel derived La-doped PbTiO3-containing films

Abstract A series of sol-gel derived La-doped PbTiO3-containing films was prepared on platinized Si wafers. The compositions investigated include PLT (0-28 mole % La) and PLZT (e.g., 9/65/35 and 12/80/20) films. These films were fired at temperatures ranging from 500 to 750°C. While most of the films were single-phase perovskite when fired at 700°C, lower firing temperatures (∼500°C) are sufficient to obtain crystalline PLT films, especially when the La content is more than 15 mole %. The paraelectric or ferroelectric character of the films as a function of La content is also addressed. In PLZT films, the Zr/Ti ratio affects the crystallization behavior and also the perovskite structure, i.e., either tetragonal or rhombohedral. Ferroelectric PLZT films exhibit high values of both dielectric constant (>700) and leakage current. The values of dielectric constant in the relaxor PLZT films are low, especially when compared to their bulk ceramic values (5000–10000). Paraelectric PLT films exhibit high values o...

Surface planarity and microstructure of low temperature silicon SEG and ELO

Surface planarity and epi/SiO2 interface characteristics of selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO), deposited at 800–950 °C/10 or 25 Torr, have been studied for micron-sized structures. SEG at 860 °C showed superior planarity and reduced ratio of facet width to epi thickness, compared to higher deposition temperatures. Data showed that epi/SiO2 interface defects are greatly reduced for structures parallel to (100) and/or by adding HCl to the source gas, compared to interfaces positioned at standard orientation (110) on a (100) substrate. The transition from SEG to ELO in view of the facet orientations will be discussed. To correlate structural with electrical data, n+/p diodes were fabricated on as-grown and polish planarized SEG. Leakage current values of approximately 100 nA/cm2 could be measured. These are comparable to similar n+/p junctions fabricated on conventional epi.

Evaluation of passivated ion implanted planar silicon detectors for the spectroscopy and assay of low energy electrons

The passivated ion implanted planar silicon (IIPS) detector is, in comparison to other semiconductor charged particle detectors such as the silicon surface barrier (SSB) detector, characterised by a thin entrance window and by low leakage current and hence low electronic noise. For the detection of low energy electrons (≲ 200 keV) it has, therefore, the potential of superior sensitivity and energy resolution. Measurements have been made at room temperature with an IIPS and a SSB detector of similar specifications of the continuous β − spectra from a 14C source (maximum energy: 156 keV) and of the line spectra from the conversion electrons of a 99mTc source. The sensitivity of a thin window (1.5–2.0 mg cm −2 mica) Geiger to 14C was also investigated. The leakage current, rms noise and capacitance characteristics as a function of the reverse bias voltage were studied for both semiconductor detectors. The IIPS had a sensitivity to 14C β − detection 26% higher than the SSB and the IIPS with an added light-tight cover had a sensitivity essentially similar to the Geiger. For 119.5 keV conversion electrons, the IIPS had a FWHM of 10.6 keV whereas that for the SSB was 15.0 keV. The rms noise, capacitance and, in particular, leakage current values were lower for the IIPS.

Natural contamination test of insulators with DC voltage energization at inland areas

Results of tests for natural contamination of insulator strings in inland areas are discussed. Natural exposure tests with -280 kV DC voltage energization were carried out for 5 years. The following results were obtained: (1) The amount of contaminant on the bottom surface increased with the length of the exposure period, for the first year, at inland areas. Therefore, estimates of contamination severity should use data obtained for exposure periods of at least one year. (2) Insulators near the line and ground sides of a string collect more contaminant than the middle when DC voltage is applied. However, the effect of nonuniform contamination on DC withstand voltage is not as great as expected when ratios of the number of heavily contaminated insulators to that of insulator string are from 15% to 30%. (3) No significant effect of DC voltage energization on the ESDD of the middle part of insulator strings has been observed when the applied voltage is no higher than 280 kV DC. (4) A pollution severity map established for AC transmission lines can be used for the determination of design ESDD for HVDC transmission lines for inland areas without industrial contamination. (5) The maximum value of leakage current under natural conditions is less than 3 mA, and no flashover has been experienced during these 5 years for electrical stress from 90 to 120 kV/m. The application of these results to insulation design for HVDC transmission lines is discussed. >

Thin-film, accumulation-mode p-channel SOI MOSFETs

Electrical characteristics of thin-film (100nm), accumulation-mode SOI p-channel MOSFETs are reported and compared to simulation. In the OFF regime, the p-type channel is fully depleted. As a result, very low values of leakage current are obtained. Very good threshold voltage control is also obtained.

Electron diffusion and leakage currents in magnetically insulated diodes

The diffusion of stochastic electrons and the associated leakage current is investigated for magnetically insulated diodes and gaps. The model system is planar and periodic in the drift direction of the electrons. The stochasticity results from periodic perturbations of nonrelativistic, constant-density equilibria. When the perturbation is sufficiently large to generate a globally stochastic region containing the electron source, a leakage current is established. The steady-state Fokker–Planck equation is solved using quasilinear diffusion coefficients. The resulting distribution is normalized to the globally stochastic fraction of the equilibrium electrons to obtain the leakage current. For realistic perturbations, the analysis yields leakage current values that are in good agreement with earlier experimental results. A ‘‘supercritical’’ insulating field, which is a function of the perturbation parameters, is calculated.

Ga0.47In0.53As field-effect transistors with a lattice-mismatched reduced leakage current GaAs gate

A lattice-mismatched GaAs gate Ga0.47In0.47As field-effect transistor (LMG-FET) with significantly reduced reverse gate leakage current is reported. The mechanism responsible for this reduction by over two orders of magnitude over previous work has been identified; it is attributed to the confinement of misfit dislocations originating at the GaAs/InGaAs interface. The LMG-FET had a gate leakage current of 0.48 ?A at ? V, and an extrinsic DC transconductance of 104 mS/ mm for a 1.4 ?m gate length and 240 ?m gate width. Further refinements in crystal growth should lead to even lower values of leakage current, making this technology attractive for high-speed logic, as well as lightwave optoelectronic integration.

Review Of Analytical Methods For Calculating The Performance Of Large Grounding Electrodes PART 1: Theoretical Considerations

The equations on the computation of grounding system performance presented in most of the papers are based on two basic concepts: the calculation of the leakage current in different linear segments of a grounding electrode, and the use of these leakage current values to find the potential at any desired point around the ground electrode layout. Generally most of the papers published have not been easy to understand. They are based on the fundamental electromagnetic concepts and some additional assumptions. This paper summarizes the analytical review of the different methods and identifies the differences among them. The question of applicability and accuracy is discussed in a companion paper [1].

A Method to Determine the Density of Surface States and Interfacial Charge Density in N-Channel Sos Mosfet's

ABSTRACTA method to determine the density of surface states NSS and interfacial charge density QSAP in n-channel silicon-on-sapphire MOS transistors from back channel leakage current measurements is presented. A rigorous theory to determine this current as a function of drain-to-source bias, VDS and as a function of body-to-source bias, VBS is also discussed. The evaluation of leakage current is more rigorous in this work because the surface potential is explicitly calculated from the charge neutrality equation of the device. The surface potential, being dependent on interfacial surface state density and the doping density, is more accurate when evaluated from the charge neutrality equation than from assuming a simple a priori value (ɸs={3/2}ɸF). Applying the present theory to experimentally reported leakage current values, the following were obtained:

Ar ion bombardment effects of NbN/Pb Josephson junctions with plasma oxidized barriers

Details of the relation between Ar ion bombardment effects on NbN surface and I-V characteristics of NbN/Pb junctions with plasma oxidized barriers have been studied. NbN base electrodes, which behave as a strong coupling superconductor (Tc>15 K, 2Δ/kTc=4.2–4.3), were prepared onto substrates at 300 °C by reactive dc magnetron sputtering. In the NbN/Pb junction fabrication, cathode self-bias voltage VCSB during Ar sputter cleaning strongly influences the subgap leakage current value, which increases with VCSB . The VCSB also influences normalized normal tunnel resistance ARNN. It is found, in reflection electron diffraction and x-ray photoelectron spectroscopy studies, that the Ar ion bombardment at VCSB> 200 V on a NbN surface produces an amorphous structure in the surface layer. It is also found that the thickness of amorphous layer increases with Ar ion energy. Based on the experimental results, low subgap leakage current junctions, where Vm exceeds 100 mV at 4.2 K, were fabricated under low energy plasma oxidation conditions, where Vm is the product of Josephson critical current and subgap resistance. Sputter cleaning and plasma oxidation conditions for obtaining high quality junctions are also discussed.

Rapid Anneal of Radiation-Induced Silicon-Sapphire Interface Charge Trapping

The rapid ahneal phenomenon of the radiation induced charge trapping at the silicon sapphire interface was experimentally investigated using a junction FET structure from 10 ?sec through 1 second after an ionizing radiation pulse for various fabrication parameters and bias conditions. The fabrication parameters investigated include type of starting sapphire (Czochralski, ribbon, and gradient furnace), sapphire polish, pre-epitaxial anneal environment (air and hydrogen), and epitaxial growth method (uniform and burst). The back channel rapid anneal effect was also characterized as a function of bias applied to the device during the radiation pulse as well as the bias applied during the anneal time. The results show that the rapid anneal time constant is essentially independent of the bias applied during the radiation pulse as well as during the anneal time, although the initial and final values of leakage current are functions of drain bias. The experimental results also show that the rapid anneal time constant is essentially independent of the type of starting sapphire, but is a function of the pre-epitaxial sapphire anneal environment and epitaxial growth method.

On the origin of leakage currents in silicon-on-sapphire MOS transistors

n-channel n-p-n metal-oxide-semiconductor transistors (MOST's), fabricated in thin films of silicon-on-sapphire, exhibit values of source-to-drain leakage currents (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> )which vary from wafer to wafer, typicaily from 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-11</sup> to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> A/mil of channel width. Conversely, p-channel (p-n-p) devices exhibit low leakage current values in the range of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-11</sup> ∼ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/mil of channel width, consistent from wafer to Wafer. A model of a high concentration of donorlike states in the silicon in the vicinity of the Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> -Si interface creating a back-surface Conductive channel is proposed to account for both the inconsistently high n-channel and consistently low p-channel leakage current values. Experimental measurements of I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> , which support the general conclusions of the model, are presented. I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> is shown to be a strong function of a) the annealing temperature of the sapphire substrate prior to film growth, b) the silicon-film growth rate, c) the impurity concentration profile in the channel region, and d) the device geometry. These measurements show that the dominant factor controlling the overall magnitude of I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> is the state of the Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> -Si interface immediately prior to silicon-film growth. A set of silicon-film growth conditions and device processing steps is outlined which achieve consistent n- and p-channel leakage current values of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> A/mil of gate width.

Ionizing Radiation Effects in SOS Structures

The total ionizing radiation effects of n-channel enhancement mode silicon on sapphire MISFET's have been characterized up to a total dose of 107 rads (Si). The drain current versus drain voltage characteristics of the n-channel devices showing the "kink" effect were measured over a range of gate voltages and as a function of ionizing radiation. The effect of the ionizing radiation on the "kink" phenomenon was determined and the implications of this effect on the radiation hardness of n-channel MISFET's is discussed. The results show that the equivalent threshold voltage at the operating drain voltage must be defined and used in determining the radiation hardness of the n-channel device. The radiation induced back channel leakage currents of n-channel MISFET's are characterized in terms of device geometry and the amount of radiation induced trapped charge in the sapphire substrate. Results showing the leakage current plotted as a function of drain voltage suggest that the "kink" effect and related phenomena also enhance the radiation induced leakage current effects and lead to substantially increased values of leakage current.

Electrolytic Determination of Porosity in Gold Electroplates: II . Controlled‐Potential Techniques

Anodic polarization curves of gold and gold‐plated copper specimens have been obtained at a sweep rate of 10 mV/min in electrolyte. The curves obtained are found to be linear over ranges of potential approaching 50 mV displacement from the free corrosion potential. From the data obtained, values of the free corrosion potential, the polarization admittance, and the leakage current are extracted and compared for each specimen. Agreement between the corrosion potential and polarization admittance values is excellent. It is shown that the polarization admittances of gold‐plated copper specimens in vary with the apparent exposed area fraction of copper according to expressions derived by Stern. Agreement between the corrosion potential and leakage current values is fair, becoming poorer as the polarizing potential is displaced farther from the free corrosion potential. It is shown that at a given value of the polarizing potential, leakage currents passed by gold‐plated copper specimens in vary directly with the apparent exposed copper area. Anodic current densities and minimum limits of detectability for the various techniques are discussed.

Implications of ion implantation technology on ion implanted active devices in silicon

Abstract The use of ion implantation to make integrated devices in silicon implies a good knowledge of the behavior of various parts of the device. This paper deals with three main topics: First the electrical characteristics of implanted diodes are described and their variations as a function of annealing temperature lead to a physical model taking into account the anisotropy of impurity concentration gradients. Second, experimental conditions before, during and after implantation are shown to have a strong influence on the quality of the final device, particularly on the value of the reverse leakage current. Third, effects of bombardment on silicon dioxide layers are studied. It is found that recovery of the layers is generally complete after a 300°C annealing. Contributions of these various parameters to the overall electrical characteristics of ion implanted self-aligned MOS transistors are finally considered. Substantial increase in the maximum oscillation frequency and reduction of the active surfac...

がいしの自動注水洗浄の一方式

This paper describes a method of automatic washing for salt contaminated insulators. An average value of leakage current along the surface of the pilot insulator in a period is detected, for this is a function of the quantity of salt contamination and moisture on the pilot insulator. In each cycle (about 1min. per cycle), the program signals give one by one the instructions on a start and an end of the integration of leakage current, a detection of the integrated value, a stop of the washing action and a reset of the integrator. Here the integrator consists of RC circuit and the detector consists of the silicon controlled rectifier (SCR) whose firing voltage is used as a reference value. If the integrator output proportional to the average value of leakage current rises above the firing voltage of the SCR, a signal of washing is sent to the pump motor or the valve. Then the insulators on line are washed all together during the appointed period.Finally, by the various experiments this method was proved to have enough accuracy and reliability for practical use. The conclusions are summarized as follows.(1) An average value of leakage current is justified to be the detecting variable.(2) The RC circuit used as the integrator is proved to be easy in maintenance.(3) Because of the fairly short period of the detecting action, the insulator is kept in a sufficiently safe condition under expected environment.

Vacuum deposition of dielectric films for capacitors

The first part of this work deals with the evaporation of inorganic materials suitable for making thin dielectric layers for capacitors. The evaporation of a mixture of oxides, for example a glass, is also discussed, and the electrical properties of some glasses are given. The stability of metal oxide compounds at high temperatures is considered in relation to their free energies of formation. The reported vapour pressures of the components of the more commonly used glasses show that their evaporation is not possible from a single vapour source without separation of the components by fractional distillation. The second part of the report describes an experimental investigation into the preparation and properties of dielectric films of silicon oxide in the thickness range 0.14 to 1.7 μ produced by the evaporation of silicon monoxide at varying rates. Capacitors of 0.001–0.01μF/cm 2 have been deposited on ‘Pyrex’ glass using evaporated aluminium films for the conducting-plates, and measurements of the electrical properties of the silicon oxide films have been made. The working voltage of capacitors in this range lies between about 12 and 60 V depending upon the thickness of the dielectric and upon the working temperature. At temperatures above 200°C the values of loss angle and leakage current are generally unacceptable. It is established that the rate of deposition of the oxide layer has a marked effect on the loss angle, dielectric constant and leakage current. Generally the lowest values of leakage current and loss angle are obtained with rates of deposition below 5Å./s. The dielectric constant of slowly deposited silicon oxide films is less than that of bulk silica, which is attributed partly to their lower density. The work carried out with silicon oxide shows that satisfactory dielectric films for capacitors can be made by the evaporation technique.

The maximum voltage, current and power ratings of junction transistors

The paper discusses the properties of a junction transistor which determine the limits of the three basic ratings, namely the maximum collector voltage, collector current and power dissipation, and describes methods of measurement. The effects of the limitations on the various circuit configurations are also discussed.The maximum value of both the direct and alternating voltages that may be applied to a transistor are dependent upon the variation of the characteristics with voltage. The most important of these factors are surface leakage, avalanche multiplication and collector/ emitter punch-through. The last is an absolute limitation whereas the first two result in a variation of the current gain and output impedance. The effects of these variations are very dependent upon the circuit arrangement and the possible parameter tolerances. The collector leakage current can also result in thermal instability. In general the important value of the leakage current, from the circuit-performance aspect, is that at high temperature. However, to simplify measuring and for life considerations, a low-temperature test may be more suitable.The maximum current rating is normally determined by the decrease in current gain at high emitter currents. Again this limitation is dependent upon the circuit arrangement and it is not possible to set an absolute limit. For linear-amplifier applications the variation of current gain with emitter current should be low, whereas, in switching applications, only the gain at high current is of importance.The power dissipation rating of a transistor is basically determined by the effect of a high internal temperature on its life. However, a convenient method of expressing the rating, as a function of ambient temperature, is by means of a maximum junction temperature and a thermal resistance. Since the total thermal resistance is dependent upon the mounting arrangements, the user must consider both the electrical and thermal properties of any transistor circuit. The transient power rating of a transistor is also of importance in many switching circuits.

An accelerated ageing experiment on germaniump–n–palloy-type transistors

A total of 660 transistors, purchased to a specification involving 100% initial testing, including damp heat cycling, have been placed on life test in groups with junction temperatures at 50, 60, 70, 80, 90 and 100°C, with power dissipations such as to give junction temperature rises of 0, 10 or 20°C above the temperature of the mounting, and with collector voltages of 0, ߝ1, &#20134 and some of ߝ20 volts. From the data so far accumulated and analysed it appears that most of the units will end their lives owing to excessive rise of collector leakage current, that there is no significant correlation between life and initial value of collector leakage current, and that positive correlation exists between deterioration of noise figure at 1 kc/s and deterioration of leakage current, the deterioration being markedly more common for units aged at the higher voltages.