Lead Pitch Research Articles

Influence of electric field, liquid film thickness, and sodium chloride deposition on atmospheric corrosion of Cu

Printed circuit boards (PCBs) are prone to failure due to the influence of environmental factors such as humidity, salt spray, and electric fields during usage. As the lead pitch of PCBs decreases and these environmental factors become challenging to control, corrosion becomes unavoidable. This study used a self-built thin liquid film–electric field coupling environment in an in situ electrochemical testing apparatus. PCB-Cu electrodes were evaluated using open-circuit potential and polarization curve tests on the thin liquid film. This study systematically investigated the effects of external electric field bias, sodium chloride deposition, and liquid film thickness on PCB-Cu corrosion. The results showed that increased bias promoted Cu corrosion in the coupled environment and altered electrode reactions. The cathodic process transitioned from activation control at 0–1 V to hydrogen evolution electrochemical control at 3 V for electrode reactions. Increased sodium chloride deposition enhanced the Cu corrosion rate in the coupled environment primarily due to Cl− damaging the corrosion product film. Under different liquid film thickness conditions, the corrosion rates can be ranked as 200 μm > 300 μm > 100 μm, with 200 μm exhibiting the highest corrosion rate and marking the transition point from the cathodic to anodic control of the corrosion reactions. Orthogonal analysis results indicated that bias was the most influential factor affecting Cu corrosion, followed by liquid film thickness and sodium chloride deposition.

The effect of gear-manufacturing quality on the mechanical and thermal responses of a polymer-gear pair

Abstract Gear-manufacturing quality affects the load sharing between the meshing gears as well as the load distribution along the width of the tooth. This study aims to investigate the effect of gear-manufacturing quality on the mechanical and thermal states of polymer-gear pairs and consequently on their lifetime. The deviations of the geometric quality parameters, i.e., the lead profile and pitch, were found to have a substantial effect on the stress (root and flank) state of the gear. The effect of the lead deviation was found to be most pronounced for the quality grades Q12 to Q10, where depending on the load, a 30–80% stress reduction was observed when improving the gear quality from Q12 to Q10. Improving the quality from Q10 to Q8 did not lead to a substantial improvement in the load distribution and the observed stress reduction was in range of 5–20%. Similar trends were found for the pitch deviation, where again the most pronounced stress reduction was seen when improving the quality grade from Q12 to Q10. The study reveals where the most effective changes, leading to an increased gear-life, can be achieved. Improving the gear quality grade from Q12 to Q11 proved to have a much more substantial effect than improving the gear quality from Q9 to Q8. Considering that improving the gear quality from Q12 to Q11 or even Q10 can be achieved by a proper tool design and corrective iterations with the right process parameters, while improving the quality from Q9 to Q8 is by far more challenging. A novel methodology is proposed to assess the effect of the gear’s quality on the generation of heat and the resulting operational temperature. The proposed methodology enables more accurate prediction of the gear pair’s operating temperature.

Wettable flank routable thin MicroLeadFrame for automotive applications

Driven by the higher power density and harsh environments in automotive, leadframe package has been varied to meet the higher requirement of reliability and integration. Quad Flat No-Lead (QFN) packages is known to provide the small form factor, and adequate for the high power package system. However, due to its wet pad characteristics, the solder volume is thin without fillet endangering the structural reliability. Therefore, it is very important to ensure structural integrity by constructing sound solder fillet, and it is mandatory for industry to inspect visually the soldering state after the bonding process. Wettable flank QFN is designed for this particular purpose. In this study, the routable thin MicroLeadFrame®, an wettable flank technology which allows easy process by employing chemical etching yet enables the side solder visible inspection for fine lead pitch, is introduced and explored. Process to achieve the wettable flank structure was developed, and the reliability was studied through Automotive Electronics Council (AEC) reliability test under package level and board level. Also, mechanical shear test and simulation was carries out to verify the wettable flank structure feasibility to the automotive electronics packaging by demonstrating excellent reliability performances.

Study of laser texturing assisted abrasive flow finishing for enhancing surface quality and microgeometry of spur gears

This paper reports on study of laser texturing assisted abrasive flow finishing (LT-AFF) process of the hobbed spur gear (HSG) to further improve their microgeometry, surface finish, micohardness, microstructure, wear resistance, and material removal rate (MRR) as compared to AFF process. Preliminary experiments were conducted to identify optimum values of power and focal length of the continuous fiber laser of 1064-nm wavelength, and number of passes for laser texturing of the HSG made of 20MnCr5 alloy steel. Identified optimum values were used to produce homothetic texture on flank surfaces of HSG in a direction perpendicular to the lay profile generated by hobbing. Influence of laser texturing was studied by comparing deviations in microgeometry, average and maximum surface roughness values, microhardness, wear resistance, and MRR of HSG directly finished by AFF and laser-textured hobbed spur gears (LTHSG) finished by AFF. Previously optimized value of viscosity of AFF medium was used during finishing of HSG and LTHSG. Deviations in total profile, total lead and total pitch, and radial runout were used to indicate deviation in microgeometry of the spur gears. Results reveal that AFF of LTHSG reduced surface roughness and errors in microgeometry and improved microhardness, microstructure, wear resistance, and MRR than direct of AFF of HSG. Improved microgeometry and surface quality of spur gears will lead to their increased operating performance and service life thus reducing their running noise and vibrations and preventing their premature and failures. This research proves that productivity of AFF process can be improved significantly by laser texturing for finishing the spur gears.

A Nonlinear Structural Analysis for Optimization of Lead Pitch in COF Bonding

A Nonlinear Structural Analysis for Optimization of Lead Pitch in COF Bonding

New Kelvin Test Socket from Aries Ideal for Low Resistance Testing of Devices with Lead Pitch down to 0.4 mm

New Kelvin Test Socket from Aries Ideal for Low Resistance Testing of Devices with Lead Pitch down to 0.4 mm

Hybrid Interconnection Process Using Solderable ICAs (Isotropic Conductive Adhesives) with Low-Melting-Point Alloy Fillers

In order to overcome several crucial limitations to the traditional electrically conductive adhesive bonding used in the electronics field, a novel low-melting-point alloy (LMPA)-filled ICA (Isotropic Conductive Adhesive) was synthesized. Also, a hybrid interconnection process using it was developed, which can be achieved by melting-coalescence-wetting behavior of LMPA fillers in ICA. In order to ensure excellent coalescence and wetting characteristics of the LMPA filler particles, the fluxing capability of the resin should have been sufficient to remove the oxide layer on the surfaces of the filler particles and the electrode materials. The effect of reductant on the hybrid interconnection formation was examined. ICAs with and without reductant were formulated with a 40% volume fraction of filler. The QFP chip had a size of 14 � 14 � 2:7 mm and a 1 mm lead pitch. The test board had a 18 mm thick Cu daisy-chained pattern. Thermal characteristic of the ICA was observed by differential scanning calorimetry (DSC), and the temperature-dependant viscosity characteristic of the polymer matrix was observed by torsional parallel rheometer. Based on the results, the reflow profile of the interconnection process was determined. The dipping interconnection method was applied in the QFP bonding process. After the QFP bonding process, the electrical characteristic of ICA was measured with a multimeter. The wetting, bondability, coalescence characteristics of the LMPA filler particles and the morphology of the conduction path were observed by microfocus X-ray inspection systems and optical microscopy. As a result, the LMPA-filled ICAs with reductant had stable contact resistance, forming the metallurgical interconnection. A good electrical conduction path was achieved with the coalescence and wetting characteristics of the molten solder particles in the ICA. [doi:10.2320/matertrans.M2009109]

Propensity of Copper Dendrite Growth on Subassembly Package Components Used in Quad Flat Package

Cu dendrite growth of quad flat package linked to epoxy molding compound (EMC), leadframe, and leadframe adhesive tape is comprehensively investigated. Cu dendrite grows particularly in the lead pitch smaller than les 130 mum covering with a leadframe tape, and in turn, it results in a resistive short. Such an appearance is attributed to test procedure of the precondition (30degC/60% relative humidity with 260-degC reflow) followed by biased stress test (125degC/1.95 V), which not only allows moisture condensation in the tape and but also provides bias between the leads. The influences of impurity in EMC and adhesive tape on dendrite formation are quantified with SEM-EDX, Auger electron spectrometry (AES), inductively coupled plasma-mass spectrometry (ICP-MS), and ICP-AES. As a result, the usage of nonhalide EMC can provide more reliable margin than that of larger lead spacing against Cu dendrite growth.

Effects of lead widths and pitches on reliability of quad flat package (QFP) soldered joints

The finite element method(FEM)is used to analyze the effects of lead widths and pitches on reliability of soldered joints.The optimum simulation for QFP devices is also researched.The results indicate that when the lead pitches are the same,the maximum equivalent stress of the soldered joints increases with the increasing of lead widths,while the reliability of the soldered joints reduces. When the lead widths are the same,the maximum equivalent stress of the soldered joints doesn't decrease completely with the increasing of lead pitches,a minimum value of the maximum equivalent stress values exists in all the curves.Under this condition the maximum equivalent stress of the sol- dered joints is relatively the least,the reliability of soldered joints is high and the assembly is excel- lent.The simulating results indicate the best parameter:The lead width is 0.2 mm and lead pitch is 0.3 mm(the distance between two leads is 0.1 mm),which are benefited for the micromation of QFP devices now.The minimum value of the maximum equivalent stress of soldered joints exists while lead width is 0.25 mm and lead pitch is 0.35 mm(the distance between two leads is 0.1mm),the devices can serve for a long time and the reliability is the highest,the assembly is excellent.The simulating results also indicate the fact that the lead width is 0.15 mm and lead pitch is 0.2 mm maybe the limit of QFP,which is significant for the high lead count and micromation of assembly.

A numerical failure analysis on lead breakage issues of ultra fine pitch flip chip-on-flex and tape carrier packages during chip/film assembly process

As the lead pitch gets finer, numerous problems emerge during manufacturing process of LCD packages. Lead breakage failure at ultra fine pitch (around 30 μm and under) chip/film assembly stage would be one of them. In this paper a failure analysis process on this issue is presented. In order to figure out more detailed phenomena that occurred at miscellaneous area for a very short instant, a numerical approach is utilized along with tests and measurements. A verified/predictive finite element model is developed and applied on flip chip-on-flex and tape carrier packages for LCD applications. The root causes of the lead breakage and dominant effecting factors are identified through various tests and simulations. Design/process guidelines for the packages are proposed to mitigate or remove the risk of the failure.

ＬＳＩリードフレーム材料の接続に関する研究 ５ 低温金錫接合法による銅箔リードの微細接合とその信頼性

This report considers the low melting point Au-Sn microsoldering (utilizing the Au 10 mass %-Sn eutectic ; melting point/ 490 K, bonding heat tool temperature/523 K and bonding time/5 s) which is applied to the 400-600 pin count and 0.10-0.15 mm lead pitch connection with 0.018 mmt thin copper lead. This method is performed by heat and press tool gang bonding of tin electroplated (3.5, μ mthick) copper pattern on substrate and gold electroplated (0.5, μm thick) thin copper lead with non flux in air. Au-Sn microsoldered layer has the high peel strength and has the high reliability in 218 K×30 min-423 K×30 min temperature cycle test and 423 K storage test in air that is higher than 37 mass % Pb-Sn microsoldering. As a result of this reserch, it is determined that the low melting point Au-Sn microsoldering is an excellent method for thin copper lead micro connection to the copper pattern routed substrate and the board.

微小ピッチＴＡＢ／ＯＬＢ技術

Novel OLB technology onto PWB at 0.15mm lead pitch by means of soldering method has been developed. This technology includes two types of OLB structures which can be adopted for many kinds of applications. One is a lead-forming type in which leads are bent in the shape of gull wings, and the other is a non-lead-forming type. In the technology, the outer leads are connected to the PWB electrodes only with electro-plated solder on the outer leads, through non-cleaning process. It was confirmed that the samples using the developed tech-niques showed good results in terms of reliability and this OLB system proved to be a practical use level.

An investigation of process parameters in the dam-bar cutting of integrated circuit packages

The rapid evolution of micorelectronics is placing greater demands on the packaging technology of integrated circuits (IC), the trend being towards higher lead counts, smaller lead width, finer lead pitch and thinner leadframes. These demands impose stringent requirements on the quality of dam-bar cutting, the latter being a mechanical trimming process in which the dam bar btween the leads of an IC package after post-molding process is pierced out. The leadframe thickness and the area of cutting are in the order of one tenth of a millimeter and cutting is performed at a much higher speed than that found in conventional blanking and piercing processes. In this work, a purposely built single-punch dam-bar cutting press was constructed. The effects of percentage punch-die clearance, punch shear and the plastic anisotropy of the leadframe materials on the cutting force and energy, and the quality of the sheared edge of the dam-bar, were studied. The optimum punch-die clearance for minimum cutting energy was established. The cutting force, energy and burr height were found to be affected by the plastic anisotropy of the virgin leadframe materials. These findings can be applied in the design of trimming tools used in the dam-bar cutting of IC packages.

ＴＣＰリードの金錫接合部の強度特性 ＬＳＩリードフレーム材料の接続に関する研究 （第４報）

This report considers the low melting point Au-Sn microsoldering (bonding heat tool temp. 523 K and time is 5 sec.) which is applied to the 400 pin count and 0.2 mm lead pitch TCP (Tape Carrier Package) assembling. This method is performed by heat and press tool gang bonding of tin electroplated (6.5 μm thick) copper pattern on substrate and gold electroplated (1.0, μm thick) TCP outer lead with non flux in air. Au-Sn microsoldered layer has the high peel strength and has the high reliability in 423 K storage in air that is higher than Sn-37 mass%Pb microsoldering. And the organic glass-epoxy (FR-4) substrate is not damaged after the Au-Sn microsoldering.

Design of 0.35-mm pitch QFP lead and its assembly technology

The solder joint reliability of a 0.35-mm lead pitch, 42-mm wide/spl times/42-mm long/spl times/23-mm high, 396 pin, ceramic quad flat package (QFP) was studied in terms of: 1) finite element analysis simulation; and 2) temperature cycling tests between -65/spl deg/C and +125/spl deg/C. Using the study results, physical design of the QFP leads, in terms of thickness, standoff, and Au surface finish were optimized. If the von Mises stress of a QFP solder joint can be optimized to be no more 16.7 kilogram square millimeter, we can guarantee QFP solder joint reliability over requested design life. Also, we developed a thermocompression (T/C) soldering process for the QFP. >

A "CLOSED LOOP" SYSTEM FOR THE REALTIME CONTROL OF SOLDER PASTE STENCIL PRINTING

The move towards fine and ultrafine pitch components in surface mount Printed Wiring Board (PWB) assembly has increased the importance of the solder paste printing process. The quality of the solder paste deposit is influenced by factors such as the characteristics of the board, the solder paste selected, the printer used, etc. These inter-related process and material factors complicate the procedures and the reasoning used to identify and set-up the stencil printing parameters. The increased use of ultrafine pitch components (with lead pitch down to 0.4 mm) in PWB assembly has almost made it mandatory to inspect the solder paste deposit prior to component placement. This inspection process provides the necessary information to correct the printing process in a realtime fashion if printing is out of control or is exhibiting a tendency to go out of control.This research designed and developed a "closed-loop" system for realtime control of the solder paste stencil printing process. This knowledge based process control system interfaces with a stencil printer and a laser based solder paste inspection system to form the "closed-loop". This "closed loop" realtime system insures both proactive and reactive control of the stencil printing process.

Inner lead gang-bonded devices with stacked Ni-Au bumps

Tape automated bonding (TAB) is a technique which is characterized by a small lead pitch, a small size, and a good high frequency behavior. To bond the inner leads of the TAB foil on the straight wall bumps on the integrated circuit (IC), thermocompression gang bonding is usually applied. If simple thin silicon nitride passivation layers are used, cracks are often observed in the sputtered TiW barrier layer (beneath the bump) and in the passivation layer of the IC. A theoretical model has been used to describe the deformation of the bump-lead structure. Comparison of this model with experimental results of the cracking behavior shows that both stress and strain at the bond pad-bump interface exceed the critical values for cracking. Plastic deformation at the bondpad is avoided if a two layer Ni-Au bump structure is used. While the plastic deformation required at the bond interface is kept constant, nickel layers with a thickness of at least 10 /spl mu/m are required to avoid even the smallest cracks. If the gold layer thickness is at least 15 /spl mu/m, the resulting bond strength is comparable with that of standard gold bumps. Deformation of the leads is restricted within acceptable limits, and the long-term reliability is not affected. Accelerated testing has been performed by high temperature storage, pressure cooker and air-to-air temperature shock testing. >

Development of a soldering/inspection workcell for surface mount devices

The small focused spot size and localized heating possible with laser soldering makes it an attractive alternative technique for bonding surface mount devices with small lead pitch onto a printed wiring board. Using a Nd:YAG laser, we have applied this technique to reflow soldering of a test device-a 224-pin quad ceramic chip (lead spacing 25 mil)-onto pretinned substrates. The soldering step was incorporated into a larger workcell, in which an Adept robot was used to place the component in position and also to scan the laser beam, delivered via a fiber, over the leads to be soldered. The mobile laser head was modified to accept a miniature CCD camera coupled to a Cognex vision system, which allowed coincident viewing of the soldering process and postsoldering inspection of the joints.

Laser system for fine pitch Tape Automated Bonding

A system has been developed for implementing a solderless fine pitch Tape Automated Bonding (TAB) process. The process was applied to multichip module (MCM) packages with lead pitch of 100 μm. The technology can be extended to ultrafine pitch as low as 25 μm and can be used for both inner lead bonding and outer lead bonding. The technology is based on metal to metal diffusion at the lead to pad interface using a ‘‘hot’’ tip energized by a laser. A closed end flat tip was used to comply with safety requirements and provide uniform temperature distribution across the footprint of the tip. The tip has shown no degradation during the initial testing of 25 000 bonds. The technology is much simpler compared to the solder based TAB process. It is easily controlled, does not require any pretreatment of the pads and is less sensitive to pad contamination and surface nonplanarity. It can be applied to various sets of pad-lead metallurgies such as Au–Au, Au–Sn, Cu–Au, and Ni–Au. The study shows that the process can be designed to be reworkable which makes it suitable for MCM applications.

A Heuristic Approach to Placement Sequence Identification for SMT

Surface mount technology (SMT) is being increasingly used in printed circuit board (PCB) assembly. The reduced lead pitch of surface mount components coupled with their increased lead count and packing densities have made it imperative that automated placement methods be used. However, the SMT placement process is often a bottleneck in surface mount manufacturing. A reduction in placement time in SMT will enhance throughput and productivity. This paper describes the design and development of a prototype expert system based approach which identifies ‘near’ optimal placement sequences for surface mount PCBs in (almost) realtime. The software structure used integrates a knowledge based system with an optimisation module. PROLOG is the language used in this research. The system was rigorously validated and tested. Ideas for further research are also presented.