The cascaded delayed signal cancelation (CDSC) method has attracted much attention recently as an efficient filtering technique to improve synchronous reference frame phase-locked loop (PLL) performance in grid synchronization under adverse grid conditions. The CDSC-based PLL suffers from slow transient response. Therefore, this study proposes a solution for grid synchronization under abnormal conditions utilizing an arbitrary time-delay operator to mitigate the DC offset and frequency adaptive CDSC operators for harmonic filtering. An accurate small-signal model was derived, opening the door to design the loop filter. The coefficient diagram method was adopted to systematically design the gains of the proportional–integral controller and a lead–lag compensator, yielding a faster dynamic response than the symmetrical optimum method-based design. The proposed PLL effectiveness was verified numerically under abnormal conditions, showing better dynamic and steady-state performance than other related PLLs. The proposed PLL requires less than two grid cycles to synchronize without ripples, meeting the grid code's requirement.