Lead Frame Chip Scale Package Research Articles

Application of a combined methodology for extraction of the electrical model of a lead frame chip-scale package

An ultra-miniature interconnect (IC) package such as a chip-scale package (CSP) provides a difficult challenge in electrical model extraction, particularly to multi-GHz frequencies, because the very small parasitics can easily be swamped by test fixture parasitics and/or by small measurement errors that might be negligible in a larger package. Incomplete data for the high-frequency electrical properties of package materials and small dimensional errors in physical model entry into electromagnetic (EM) simulators, again negligible in larger packages, may also cause significant error. Therefore, for ultra-miniature packages it is necessary to cross-correlate multiple measurement and simulation methods to ensure that an accurate package electrical model is obtained. This paper therefore presents a closed-loop cross-correlation of s-parameter and time domain reflectometry (TDR) measurements with EM simulation and TDR simulation for a 16-pin lead frame chip-scale package (LFCSP) and the extraction of a cross-verified electrical model to 10 GHz. The authors are not aware of the previous application of these multiple techniques to a CSP to this bandwidth.

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.

Interfacial reaction and solder joint reliability of Pb-free solders in lead frame chip scale packages (LF-CSP)

Chip scale packages (CSP) have essential solder joint quality problems, and a board level reliability is a key issue in design and development of the CSP type packages. There has been an effort to eliminate Pb from solder due to its toxicology. To evaluate the various solder balls in CSP package applications, Pb-free Sn-Ag-X (X=In, Cu, Bi) and Sn-9Zn-1Bi-5In solder balls were characterized by melting behavior, phases, interfacial reaction, and solder joint reliability. For studying joint strength between solders and under bump metallurgy (UBM) systems, various UBMs were prepared by electroplating and electroless plating. After T/C (temperature cycle) test, Sn3.5Ag8.5In solder was partially corroded and its shape was distorted. This phenomenon was observed in a Sn3Ag10In 1Cu solder system, too. Their fractured surface, microstructure of solder joint interface, and of bulk solder ball were examined and analyzed by optical microscopy, SEM and EDX. To simulate the real surface mounting condition and evaluate the solder joint reliability on board level, Daisy chain test samples using LF-CSP packages were prepared with various Pb-free solders, then a temperature cycle test (−65∼ 150°C) was performed. All tested Pb-free solders showed better board level solder joint reliability than Sn-36Pb-2Ag. Sn-3.5Ag-0.7Cu and Sn-9Zn-1Bi-5In solders showed 35%, 100% superior solder joint reliability than Sn-36Pb-2Ag solder ball, respectively.

Board level reliability assessment of chip scale packages

Abstract A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.