Application of a combined methodology for extraction of the electrical model of a lead frame chip-scale package

Abstract

An ultra-miniature interconnect (IC) package such as a chip-scale package (CSP) provides a difficult challenge in electrical model extraction, particularly to multi-GHz frequencies, because the very small parasitics can easily be swamped by test fixture parasitics and/or by small measurement errors that might be negligible in a larger package. Incomplete data for the high-frequency electrical properties of package materials and small dimensional errors in physical model entry into electromagnetic (EM) simulators, again negligible in larger packages, may also cause significant error. Therefore, for ultra-miniature packages it is necessary to cross-correlate multiple measurement and simulation methods to ensure that an accurate package electrical model is obtained. This paper therefore presents a closed-loop cross-correlation of s-parameter and time domain reflectometry (TDR) measurements with EM simulation and TDR simulation for a 16-pin lead frame chip-scale package (LFCSP) and the extraction of a cross-verified electrical model to 10 GHz. The authors are not aware of the previous application of these multiple techniques to a CSP to this bandwidth.