LDPC Decoder Research Articles

A Neural Network-Based Compressive LDPC Decoder Design Over Correlated Noise Channel

A Neural Network-Based Compressive LDPC Decoder Design Over Correlated Noise Channel

An Improved Low-Density Parity-Check Decoder and Its Field-Programmable Fate Array Implementation

Based on the IEEE 802.16e standard’s (672,336) LDPC code and the normalized Min-Sum decoding algorithm, this paper designs and implements an LDPC decoder that optimizes the channel information. The correction factor for check nodes is converted into a correction factor for the initial channel information, replacing the optimization of check node information with that of initial channel information. This achieves decoding performance equivalent to the traditional normalized Min-Sum decoding algorithm. Different correction factor values vary in complexity during FPGA implementation, as they involve different amounts of shift-add operations. For NMS decoding requiring a high number of shift-add operations to achieve optimal correction values, this can be converted into an LDPC decoding algorithm optimized for channel information, reducing computational overhead without sacrificing performance. A partially parallel improved decoder was designed and implemented on an FPGA, and its feasibility was verified using the Vivado simulation platform.

EBDN: Entropy-Based Double Nonuniform Sensing Algorithm for LDPC Decoding in TLC nand Flash Memory

EBDN: Entropy-Based Double Nonuniform Sensing Algorithm for LDPC Decoding in TLC nand Flash Memory

Advanced channel coding schemes for B5G/6G networks: State‐of‐the‐art analysis, research challenges and future directions

SummaryAs a consequence of continuing demand for additional capacity and higher quality data transmission, channel coding as a key component of a digital communication network has progressed from a classical single pair, point‐to‐point information theoretic application to a class of coding techniques with diverse parameters. The heterogeneous requirements of B5G/6G networks technology have made flexibility of code parameters the main desired feature while designing channel codes. Owing to this, channel coding techniques have evolved to support enabling applications that depend on different factors such as latency, reliability, energy efficiency and throughput. We review and discuss the application of new techniques, modifications in the design and construction of modern channel coding schemes, including block, convolutional, rateless and space‐time codes. Further, the error correction performance of mainstream channel decoders for LDPC, polar and turbo codes is compared and analysed for their attainable error rate. The aim of this study is to highlight the adaptability of the discussed coding schemes for the forthcoming cellular network landscape. This article also addresses the implementational challenges of high throughput, low latency and machine type communication scenarios. Moreover, some recent studies exploring the role of machine learning for optimisation of B5G/6G networks are classified and discussed. Concluding, research areas pertaining to the scalability of error control coding for next generation networking are addressed.

High-Throughput Polar Code Decoders with Information Bottleneck Quantization.

In digital baseband processing, the forward error correction (FEC) unit belongs to the most demanding components in terms of computational complexity and power consumption. Hence, efficient implementation of FEC decoders is crucial for next-generation mobile broadband standards and an ongoing research topic. Quantization has a significant impact on the decoder area, power consumption and throughput. Thus, lower bit widths are preferred for efficient implementations but degrade the error correction capability. To address this issue, a non-uniform quantization based on the Information Bottleneck (IB) method is proposed that enables a low bit width while maintaining the essential information. Many investigations on the use of the IB method for Low-density parity-check code) LDPC decoders exist and have shown its advantages from an implementation perspective. However, for polar code decoder implementations, there exists only one publication that is not based on the state-of-the-art Fast Simplified Successive-Cancellation (Fast-SSC) decoding algorithm, and only synthesis implementation results without energy estimation are shown. In contrast, our paper presents several optimized Fast-SSC polar code decoder implementations using IB-based quantization with placement and routing results using advanced 12 nm FinFET technology. Gains of up to 16% in area and 13% in energy efficiency are achieved with IB-based quantization at a Frame Error Rate (FER) of 10-7 and a polar code of N=1024,R=0.5 compared to state-of-the-art decoders.

Enhancing 5G LTE Communications: A Novel LDPC Decoder for Next-Generation Systems

Enhancing 5G LTE Communications: A Novel LDPC Decoder for Next-Generation Systems

Universal High-Throughput and Low-Complexity LDPC Decoder for Laser Communications

Universal High-Throughput and Low-Complexity LDPC Decoder for Laser Communications

Deep Learning Approach for Efficient 5G LDPC Decoding in IoT

Deep Learning Approach for Efficient 5G LDPC Decoding in IoT

Utilizing Multi-Body Interactions in a CMOS-Based Ising Machine for LDPC Decoding

Utilizing Multi-Body Interactions in a CMOS-Based Ising Machine for LDPC Decoding

A 4.86-pJ/b Energy-Efficient Fully Parallel Stochastic LDPC Decoder With Two-Stage Shared Memory

A 4.86-pJ/b Energy-Efficient Fully Parallel Stochastic LDPC Decoder With Two-Stage Shared Memory

Area-Efficient Non-Binary LDPC Decoder With Column-Wise Trellis Min–Max Algorithm

Area-Efficient Non-Binary LDPC Decoder With Column-Wise Trellis Min–Max Algorithm

Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Ultra-reliable low-latency communications, URLLC, are designed for applications such as self-driving cars and telesurgery requiring a response in milliseconds and are very sensitive to transmission errors. To match the computational complexity of LDPC decoding algorithms to URLLC applications on IoT devices having very limited computational resources, this paper presents a new parallel and low-latency software implementation of the LDPC decoder. First, a decoding algorithm optimization and a compact data structure are proposed. Next, a parallel software implementation is performed on ARM multicore platforms in order to evaluate the latency of the proposed optimization. The synthesis results highlight a reduction in the memory size requirement by 50% and a three-time speedup in terms of processing time when compared to previous software decoder implementations. The reached decoding latency on the parallel processing platform is 150 μs for 288 bits with a bit error ratio of 3.410–9.

LDPC Level Prediction Toward Read Performance of High-Density Flash Memories

High-density NAND flash memories have been prevailing in storage systems to achieve large capacities for explosive data. However, they suffer from more severe reliability degradation due to the narrowed margins between threshold voltage states. LDPC codes have been widely applied in high-density flash memories to ensure data reliability. Due to the increased number of cell states, more read voltages are required in reading a flash page correctly. This induces more soft levels to read pages with high bit error rates in LDPC decoding. Read latency is significantly increased in high-density flash memories. To enhance the read performance of high-density flash memories, this paper proposes PreLDPC, an LDPC level prediction approach with fine-grained LDPC reading. The key idea of PreLDPC is to predict the final read level during the early read iteration, thus avoiding unnecessary read-retry latency. From a preliminary study, we observe that after decoding in the first two iterations, the ratio of cells that lie in error-prone area (i.e. adjacent area of two cell states) can be obtained. The ratio is closely related to the final read level for a successful decoding. By exploiting this observation, PreLDPC directly uses the predicted read level for LDPC reading, which could eliminate excessive number of read retries. Furthermore, by exploiting the benefit of fine-grained LDPC reading, this paper further divides the existing integer level (called i-level, e.g. level-1 and level-2) into finer decimal level (called d-level, e.g. level-1.25 and level-1.5), and proposes a fine-grained read method. By combining the prediction method and fine-grained method together, PreLDPC can first estimate the i-level and then perform the read-retry iteration with d-levels to eliminate unnecessary read latency as much as possible. From experimental results of real-world workloads on Disksim with SSD extensions, it is verified that PreLDPC can effectively reduce read latency in high-density flash memories.

Design and Implementation of a Highly Efficient Quasi-Cyclic Low-Density Parity-Check Transceiving System Using an Overlapping Decoder.

The traditional LDPC encoding and decoding system is characterized by low throughput and high resource consumption, making it unsuitable for use in cost-efficient, energy-saving sensor networks. Aiming to optimize coding complexity and throughput, this paper proposes a combined design of a novel LDPC code structure and the corresponding overlapping decoding strategies. With regard to structure of LDPC code, a CCSDS-like quasi-cyclic parity check matrix (PCM) with uniform distribution of submatrices is constructed to maximize overlap depth and adapt the parallel decoding. In terms of reception decoding strategies, we use a modified 2-bit Min-Sum algorithm (MSA) that achieves a coding gain of 5 dB at a bit error rate of 10-6 compared to an uncoded BPSK, further mitigating resource consumption, and which only incurs a slight loss compared to the standard MSA. Moreover, a shift-register-based memory scheduling strategy is presented to fully utilize the quasi-cyclic characteristic and shorten the read/write latency. With proper overlap scheduling, the time consumption can be reduced by one third per iteration compared to the non-overlap algorithm. Simulation and implementation results demonstrate that our decoder can achieve a throughput up to 7.76 Gbps at a frequency of 156.25 MHz operating eight iterations, with a two-thirds resource consumption saving.

Research and Implementation of High-Efficiency and Low-Complexity LDPC Coding Algorithm

In this work, we proposed a high-efficiency and low-complexity encoding algorithm and its corresponding implementation structure during the design and implementation process of an LDPC encoder and decoder. This proposal was derived from extensive research on and analysis of standard encoding algorithms and recursive iterative encoding algorithms, specifically targeting the problem of high computational complexity in encoding algorithms. Subsequently, we combined binary phase-shift keying modulation mode and additive white Gaussian noise channel transmission with the min-sum decoding algorithm to realize the (1536, 1024) LDPC codec. This codec was uniformly quantized with a (6, 2) configuration, executed eight iterations, and achieved a 2/3 code rate in the IEEE802.16e standard. At the bit error rate (BER) of 10−5, the codec’s BER obtained by the proposed coding algorithm was about 0.25 dB lower than the recursive-iterative coding algorithm and was about 1.25 dB lower than the standard coding algorithm, which confirms the correctness, effectiveness, and feasibility of the proposed algorithm.

The Syndrome Bit Flipping Algorithm for LDPC Codes

Performance of LDPC decoders at high SNR is dominated by trapping sets that induce an error floor in the performance curve. We propose a new algorithm that resolves trapping sets and lowers the error floor. The new algorithm, called Syndrome Bit Flipping (SBF), computes the sum of adjacent parity violations at each symbol node. Bits are flipped by comparing the syndrome sum against a time-varying threshold called the decoding key. SBF is compared to other bit-flipping decoders on the Binary Symmetric Channel (BSC), and is demonstrated as a post-processing step for a Noisy Gradient Descent Bit-Flipping (NGDBF) hardware decoder. We demonstrate the post-processing method for an LDPC code defined in the 802.3an standard, and find that the frame error rate is improved by at least two orders of magnitude, even as the required iterations are reduced by 33%.

Hamming-Distance Trellis Min-Max-Based Architecture for Non-Binary LDPC Decoder

Limitations on hardware resource consumption and throughput make the use of non-binary low-density parity-check (NB-LDPC) codes challenging in practical applications. This paper first proposes a novel check-node (CN) decoding algorithm called Hamming-distance trellis min-max (H-TMM) to reduce the complexity introduced by searching for two minimum values in previous TMM-based algorithms. Then, by taking advantage of the proposed algorithm and the number appearances of reliable values, a high-performance H-TMM-based NB-LDPC decoder architecture is presented. Experiments on the 32-ary (837, 726) NB-LDPC code confirmed that the proposed decoder can obtain a high throughput on less hardware resources compared with the state-of-the-art works while maintaining a competitive error-correcting performance. In particular, the proposed CN unit architecture reduced hardware resources by almost half compared to that in the latest decoder.

Adaptive LDPC coded high data rate based IR-UWB combined with VMIMO system for vehicular communication links

The automotive industry is developing significantly with the evolution of vehicular networks, intelligent transportation systems, and autonomous cars. These technologies are made achievable by recent advances in software, hardware, and communication systems, along with various applications and standardization efforts. On the other side, many impairments have existed due to these evolving, limiting the process of vehicular networks. So, this paper proposes an implementation of adaptive LDPC-coded, high data rate-based Impulse Radio-Ultra Wide Band (IR-UWB) combined with Virtual Multiple Input Multiple Output (VMIMO) systems for Vehicle-to-Vehicle (V2V) and Vehicle-to-Infrastructure (V2I) wireless communications. Furthermore, they are merged with orthogonal pulse shaping using a modified Hermite pulse. Besides, the paper compares Zero-Forcing (ZF) and Minimum Mean Square Error (MMSE) detection techniques. To enhance and mitigate the existing impairments facing the vehicular networks. The proposed system’s performance is evaluated using both techniques, utilizing Bit Error Rate (BER), processing time, and resultant throughput analysis for both channel models. The simulation results include Non-Line of Sight (NLoS) and Line of Sight (LoS) scenarios for both channel models. Moreover, the simulation considers the effect of path loss and noise on the transmitted signal. In addition, the recent LDPC decoding algorithm termed “Modified Implementation Efficient Reliability Ratio Weighted Bit Flipping” (MIERRWBF) is evaluated through all latter channel models. At last, a novel adaptive LDPC decoder is proposed to further enhance the performance of all vehicular communication links under study. Consequently, the paper proposed an integrated adaptive LDPC-coded high data rate communication system to enhance vehicular communications using VMIMO mixed with modified Hermite orthogonal pulse shaping and deploying the MMSE recommended detection technique.

High-performance hard-input LDPC decoding on multi-core devices for optical space links

LDPC codes are a family of error-correcting codes that are present in most space communication standards. Thanks to their large processing power and their parallelization capabilities, prevailing multicore devices facilitate real-time implementations of digital communication systems, which were previously implemented into dedicated hardware devices. Previous works were done over the last decade on the implementation of Gbps decoders on programmable devices. However, these works focus on the soft input LDPC decoding algorithms. But, hard-input LDPC decoders are also required to design and prototype for instance next optical-based satellite communication systems. These systems should provide high throughput (≥10 Gbps) and low latency (≤1ms) internet links. In this article, the first software-based implementation of a hard-input multi-Gbps LDPC decoder is detailed. Thanks to different parallelization strategies and deeply optimized SIMD codes, throughput up to 7.5 Gbps is achieved when 10 Gallager-E iterations are executed onto an INTEL Xeon device making possible the design of software base station systems providing throughputs of tens of Gbps for optical system evaluation or base station design.