Layout Area Research Articles

An area efficient sense-amplifier flip-flop design for low power applications

ABSTRACT A novel sense-amplifier (SA) based flip-flop (FF) design is proposed to improve power and area efficiency for low-power applications. To reduce transistor count, a logic replacement technique is initially applied to the RS latch design. Following this, the discharge paths of both the sense-amplifier design and RS latch design are merged, effectively removing redundant transistors. This integration reduces layout area and addresses the additional power consumption from glitches observed in previous SAFF designs. These enhancements significantly decrease the clock-to-Q delay and average power consumption, with performance gains confirmed through post-layout simulations and chip measurements.

Data-driven optimization design method and tool platform for green residential area layout

ABSTRACT In early design stage of residential area layouts, sustainable design and performance optimization are crucial for minimizing environmental impact of buildings. This work integrates environmentally-friendly sustainable design with artificial intelligence technology to enhance residential area layouts. A parametric generative algorithm is developed to automatically generate design schemes for typical Chinese urban residential areas based on a sustainable, performance-oriented design flow. The workflow of architects is summarized into the following steps:1) Extraction of spatial form features from the residential area layout database;2) Automatic generation and sunlight duration simulation of new design schemes;3) Evaluation and screening of generated schemes. The generative algorithm is implemented using Rhino/Grasshopper, Python, and Matlab. In a case study involving residential area layouts in Beijing, the design scheme with the lowest values of DF, WinH, QuVue, SiteH, and UTCI among 42,691 automatically generated schemes was identified as the optimal scheme. This optimal scheme’s total load is 40.7% lower than the original scheme. To validate the design flow, two additional case studies were conducted. The results demonstrate that the parametric generative design of residential area layouts facilitates passive sustainable design in the early design stage and enhances environmental effects without increasing construction costs.

Analysis of high speed dynamic current mode D-FlipFlop in nanometer CMOS

ABSTRACT The advent of digital IC has increased rapidly to sustain the end-user’s requirement of high speed computation with least possible power burn to enhance the battery lifetime in portable electronic gadgets. Although CMOS serves to configure such digital logic, the switching power is found to be proportional to the operating frequency due to which MOS current mode logic (MCML) came into existence. Accordingly, this article presents a design of novel high-speed dynamic CML-based D-latch and D-FF for 90 nm process with a layout area requirement of 108.624 μ m 2 . The small signal model of proposed design is used to compute the propagation delay equation and is compared with conventional CML D-Latch and triple tail D-latch circuit to prove worth of this new architecture. The simulation using Cadence® Virtuoso with a clock of 10 GHz and V dd = 1.2 V record the power burn of 219.05 μW , delay of 31.30ps, set-up time of 12.80ps, hold time of −27.40ps and latency of 43.80ps while driven by a 2.5 GHz input datastream. Besides, the validation of proposed design is also carried out in lower technology nodes like 65 nm and 40 nm UMC where the reported parametric values could depict the design’s stable performance.

Implementasi Pendekatan Activity Relationship Chart dalam Perancangan Tata Letak Gudang Baru untuk Memperpendek Perpindahan Material di UD. M

This research discusses the issues faced by UD M, which produces crispy brownie chips, where the finished goods warehouse often becomes overcrowded due to production reaching 253 boxes, while the warehouse capacity is only 48 boxes. Due to other factors as well, the owner decided to move all activities, starting from raw material storage, production, and finished goods storage, to another location. The problem is the absence of a layout for the new warehouse. With this issue, the author designed the factory layout based on the Shared Storage method, considering material handling and the FIFO picking system. This research aims to provide the owner of UD M with considerations for arranging the facility layout in the new building. In addition to changing the layout of the finished goods warehouse, the owner plans to relocate the factory. The author reorganized the new factory of UD. M based on the results of the Activity Relationship Chart.(ARC). The research results show that the raw material warehouse, which initially measured 11.30 m², has been reduced to 10.32 m². Then, the finished goods warehouse, which initially could only hold 48 boxes, can now hold up to 123 boxes per day. By changing the layout of the production area, the production flow also becomes more organized and systematic. Keywords: ARC, FIFO, Production Flow, Share Storage, Warehouse

Novel Class-AB Operational Amplifier for Compact and Energy-Efficient Wake-Up Sensor Systems.

This paper presents a novel rail-to-rail Class-AB operational amplifier tailored for wake-up systems in motion sensor applications. By addressing limitations in free Class-AB designs, such as large inrush current, unstable bias conditions, and area ineffiiency, the proposed design achieves a gain of 59 dB and unity gain frequency of 550 kHz driving a 5 pF load. The inrush current is reduced from 1 mA to 7 µA, increasing the battery life. The layout area is reduced by 53% compared to the free Class-AB design, making it highly suitable for compact implementations. Operating at a low power consumption of 2 µW with a 1.8 V supply, the amplifier achieves a Signal-to-Noise-and-Distortion Ratio (SNDR) of 22 dB. These advancements demonstrate the potential of the design for energy-efficient analog front-end solutions in IoT and portable systems.

Design of a time to digital converter for LGAD detector at HIAF complex

The High-Intensity Heavy-ion Accelerator Facility (HIAF) is a leading platform for heavy-ion scientific research in China with advanced beam current indicators. In these experiments, Low-Gain Avalanche Detectors (LGAD) have become the detector of choice, and the readout circuit of LGAD requires time-to-digital converters (TDC) to convert the time measurement results into digital signals. Since a smaller pixel area is conducive to improving positional resolution and spatial resolution, a TDC using calibration modules instead of delay-locked loops (DLLs) is proposed to achieve lower power consumption and area. The proposed TDC is a 3-stage architecture, reaching an extensive dynamic range and a high resolution. In addition, calibration modules are used to measure the relationship between two adjacent stages of resolution. Thus, the resolution of the TDC could be confirmed under the influence of process, voltage, temperture (PVT) variation. Compared with the TDCs using DLLs, the proposed TDC reduces the power consumption and area. The resolution of the proposed TDC is about 5.13 ps, and the dynamic range is 25.2 ns. The integral nonlinearity (INL) and the differential nonlinearity (DNL) are both less than 0.3 least significant bit (LSB). Including two TDCs, which measure the time of arrival (TOA) and the time of threshold (TOT), respectively, the layout area is 931 μm × 447 μm

A high accuracy CMOS peak detection and holder ASIC for neutron detectors

With the completion and operation of a series of high-performance neutron sources, such as the China Spallation Neutron Source (CSNS), various neutron scattering spectrometers have continuously increased their performance requirements. One important aspect is to reduce collisions between scattered neutrons and air molecules during neutron scattering experiments, thereby reducing background noise and obtaining highly accurate experimental measurement results. This paper presents an application-specific integrated circuit (ASIC) dedicated to position-sensitive Helium-3 tubes neutron detector, which introduces peak detection and holder (PDH) circuits on the basis of traditional front-end electronics. Through a specific design, the switches and holding capacitor of the PDH module are isolated, ensuring that the holding voltage is not affected by switch noise, and maximizing the measurement accuracy of the PDH module. The 8 channel ASIC, realized in 0.18 μm CMOS technology, has a 10 fC to 1 pC input signal range with a linearity error within 0.22% to 1%. The PDH module is supplied with a single voltage of 1.8 V with a total power consumption of 350 μW with a layout area of 361 μm × 68 μm. The ASIC further enhances system integration, allowing the analog-to-digital conversion module to employ low-speed ADCs, thereby reducing the overall power consumption of the readout system. This enables the entire detector to operate in a vacuum environment, providing a new electronic readout solution for future neutron scattering and imaging experiments.

Development of excavator arm movement with wireless control using Bluetooth and the Internet of Things (IoT)

This research is to develop a wired control system into a wireless control system on a laboratory scale mini excavator. First step is to review the development of the drive system and control system on previous excavator models, change the pneumatic drive system to electro-pneumatic, changing the control system from wired control to wireless control using Bluetooth and Internet of Things (IoT) system. The excavator with scale 1:14 is driven by a pneumatic system. The movement of the actuator is controlled using a wired remote, so that the working area is still limited to a certain area. The pneumatic control system on previous excavators was developed into an electro-pneumatic control system. Electro-pneumatic control system by replacing the 5/2-way directional valve with a 5/3-way double solenoid directional valve. With this valve, the movement of the excavator arms can be adjusted according to the operator’s wishes. The wired control system was developed into a wires control system including the Bluetooth system and the Internet of Things (IoT). Important components in these two control systems are Arduino Mega 2560, WEMOS D1 R32, 16 channel relay, and HC05 module. The excavator model with the development of a new control system has unchanged dimensions from the previous model. The excavator arms still use the previous excavator arms as well as the traveler with the same undercarriage. Only the body housing the control system is adapted to the new component layout area. Testing the wireless remote system is at a distance of around 30 meters, while the IoT remote system at a distance of around 1.5 km. The movement of each step is easier to regulate because it uses a 5/3-way directional valve. The time used for each step is also less than previous excavator models

Design of CMOS low noise amplifier with inductive degeneration for navigation application

Abstract This paper presents an advanced Low Noise Amplifier (LNA) tailored for high-precision navigation applications, designed using the 180nm technology node and implemented in Cadence Virtuoso. The LNA features a single-ended amplifier configuration with cascaded NMOS transistors to achieve superior isolation and input matching through source degeneration, optimizing gain and noise performance. At 1.2 GHz, the amplifier achieves a gain of 33 dB and a noise figure of 1.3 dB. It demonstrates a 1 dB compression point of –16 dBm and a third-order intercept point (IIP3) of –10 dBm, with a power consumption of 44 mW from a 1.8 V supply. Post-layout simulations reflect a noise figure of 2.9 dB and a gain of 19.5 dB, highlighting practical design considerations. The layout area is 0.51 mm², underscoring the compact yet highly efficient design.

Advancing Sustainability in Urban Planning by Measuring and Matching the Supply and Demand of Urban Green Space Ecosystem Services

As global cities rapidly develop, the realization of sustainable urban development has become a pressing global concern. As a critical component of the urban built environment, urban green spaces are essential for maintaining the sustainability of urban ecosystems by offering a variety of ecological benefits. However, there are some problems in the design and construction of urban green framework, which often disregard the real needs of residents and hinder the sustainable development of urban areas. Therefore, urban planning that takes into account the supply and demand relationship of urban green space is considered to be a key technology that should help to improve residents’ happiness and promote urban sustainable development. This paper takes Zunyi City as an example; selects six indicators; combines UAV images, population, economic, and environmental data to evaluate ecosystem services valuation existing green space in the city; and analyzes its social and ecological needs. Affected by land utilization and development density, the supply value showed low spatial density characteristics in the central urban area and high spatial distribution characteristics in the surrounding urban area. The correlation between demand value and population density is the largest, and the distribution pattern is similar to that of population density. The supply-demand ratio in the study area is −0.54, indicating a severe imbalance between supply and demand. The correlation analysis between the comprehensive supply and demand ratio and each influencing factor shows that the correlation with population density is the largest. The combination of supply and demand maps addresses a major problem in planning, namely, ensuring that communities have priority in providing urban green space based on society’s need for ecosystem services. In addition, these maps will help develop the best green space planting plans to meet the specific needs of different communities. Taken together, the findings can help city planners and decision makers improve the layout of urban green areas, increase ecosystem service potential, and improve urban environmental quality and sustainability.

Volumetric drag coefficients for generic urban configurations: Insights from canopy flow analysis

Alternative drag approaches for representing unresolved buildings were proposed in literature for computational fluid dynamics (CFD) simulation of macroscopic urban airflow. As a contribution, the present work derives the volumetric drag coefficient (Cd*) through canopy drag and velocity analysis and provides appropriate correlations for Cd*against urban morphological parameters. A total of 72 cases across various urban configurations are investigated, categorized by building typology, horizontal layout, height variability, and plan area density (λp, from 0.0625 to 0.57). Reynolds-Averaged Navier-Stokes (RANS) simulations with periodic boundary conditions are performed to model fully developed flows. Results for the normalized drag force and superficial velocity and their relations with λp are evaluated. Subsequent evaluation of the profiles for the sectional coefficients (Cd*(Z)) reveals four distinct types with variations in uniform-height cases and combinations in varying-height cases. A throughout correlations analysis, facilitated by data transformation, identifies the straightforward relations between Cd* and frontal area density (λf) and tortuosity (τ). The followed stepwise regression provides a recommended formula for Cd*, demonstrating a proper fit with the simulated values. These findings facilitate the understanding and appropriate estimation of Cd* and Cd*(Z), promoting the application of macroscopic turbulence models, for neighborhood-scale wind and air quality studies.

LIC-CGAN: fast lithography latent images calculation method for large-area masks using deep learning.

Latent image calculation for large-area masks is an indispensable but time-consuming step in lithography simulation. This paper presents LIC-CGAN, a fast method for three-dimensional (3D) latent image calculation of large-area masks using deep learning. Initially, the library of mask clips and their corresponding latent images is established, which is then used to train conditional generative adversarial networks (CGANs). The large area layout is divided into mask clips based on local pattern features. If a mask clip matches one from the training library, its latent image can be obtained directly. Otherwise, the CGANs are employed to calculate its local latent image. Finally, all local latent images are synthesized to simulate the entire latent image. The proposed method is applied to lithography simulations for display panels, demonstrating high accuracy and a speed-up of 2.5 to 4.7 times compared to the rigorous process.

Addressing output ripples in low-power CMOS-based multistage DC-DC boost converters for self-powered electrochemical sensors applications

In modern electronic systems, the DC-DC converter plays a pivotal role by facilitating the conversion of direct current (DC) from one voltage level to another. Given the diverse voltage requirements of contemporary chips, a single chip may encompass multiple circuitry groupings, each necessitating specific voltage levels for optimal functionality. To address this need, voltage converters are essential, whether it involves increasing the voltage (Boost converter), decreasing the voltage level (Buck converter), or performing both functions (Buck-boost converter). This paper presents a novel multistage DC-DC converter designed to minimize voltage ripples. The proposed three-stage DC-DC converter is supplied with a 1.5-V input and achieves a four-boost ratio. The cascaded architecture integrates switching capacitors and a gyrator, complemented by a terminating low-pass filter, resulting in a minimal voltage ripple of 0.0003 % relative to the maximum output voltage. Notably, integrating the gyrator enables an inductorless CMOS-based architecture, significantly reducing layout area to 30 × 140 μm2. Furthermore, the converter's transient response was simulated, yielding a response time of 90 ms.

Assessing the Cascading Post-Earthquake Fire-Risk Scenario in Urban Centres

The frequency of urban fires has grown in recent years everywhere, especially in historic districts, including in Portugal, due to the existence of sensitive igniting materials, the proximity of buildings, the complex urban layout, and the presence of many people. The current study proposes a technique, applied in the Baixa Pombalina (downtown) area in Lisbon, to undertake an appropriate evaluation of the post-earthquake fire cascading effect, which may cause major damage. The earthquake vulnerability and damage scenario were carried out using the Risk-UE method. An empirical fire ignition model was then applied to determine the quantity and location of fire ignitions for different return periods. Furthermore, the simple fire spread Hamada’s model was applied to both the equally spaced grid buildings, as in the original Hamada procedure, and the current study area layout for different time thresholds. Finally, the risk assessment for both models was carried out, allowing for the estimation of earthquake and fire losses, respectively. The results demonstrated that the models are comparable, showing that the Hamada model might be a useful tool for large-scale evaluations aimed at disaster-risk reduction and management since it gives useful information for managing and reducing natural and anthropogenic hazards.

Design of SRAM cell using an optimized D-latch in quantum-dot cellular automata (QCA) technology

A newer nanoscale technology called quantum-dot cellular automata (QCA) has been used by researchers to design digital circuits in place of the more traditional complementary metal–oxide semiconductor (CMOS) technology. This recent development in the technology change is due to the problems faced by CMOS technology in terms of power consumption and physical limitations. The advantages of QCA technology over CMOS technology are high density, low power consumption, high-speed operation, and less footprint area. This research provides a novel circuit for D-latch and static random access memory (SRAM) cells based on QCA technology. Initially, a D-latch circuit is proposed with a layout area of 0.01 μm2, a 0.5 clock cycle delay (latency), and a cell count of 18 QCA cells. Furthermore, an SRAM cell is proposed using the same D-latch circuit, which uses cell counts of 26 QCA cells and contributes to a layout area of 0.02 μm2 with a 0.75 clock cycle delay (latency). It is observed that our proposed circuits have a smaller layout area, fewer QCA cell counts, and a lower clock cycle delay (latency) than existing circuits.

Urban expansion in highly populous East Asian megacities during 1990–2020: Tokyo, Seoul, Beijing, and Shanghai

The world is experiencing unprecedented urbanization, particularly through the continuous growth of megacities, leading to significant urban land expansion. The spatial layout and growth patterns of urban areas play a critical role in determining cities' sustainable development. However, the optimal path for cities undergoing rapid urbanization remains uncertain. This study examines four megacities—Tokyo, Seoul, Beijing, and Shanghai—and, from the perspective of urban land density, compares their patterns and processes of land expansion in 1990, 2000, 2010, and 2020. Findings reveal that the urban land area of China's megacities has expanded nearly fourfold over the past three decades. Meanwhile, Tokyo and Seoul have adopted a polycentric urban structure, becoming increasingly compact. In contrast, Beijing and Shanghai are only beginning to show signs of polycentric development. The study concludes that cities experiencing rapid growth should not impose excessive limitations on urban expansion. Polycentric and compact development has become a critical strategy for megacities. These insights offer valuable guidance for urban planning and sustainable development in both established and emerging megacities across East Asia.

Low-Temperature Drift Bandgap Reference Based on Exponential Compensation Design

Abstract In analogue and mixed-signal systems, a stable and accurate reference voltage source is essential to ensure system performance. In this paper, a high-precision bandgap reference (BGR) with a high power supply ripple rejection ratio (PSRR) and lowtemperature drift is proposed, which mainly consists of a core circuit, an exponential temperature compensation circuit, a PSRR enhancement circuit and a start-up circuit. The PSRR is improved by using a PSRR enhancement circuit and a low-pass filter. An exponential compensation circuit is used to reduce the temperature drift coefficient of the bandgap reference. Based on a 0.18 μm BCD process for design and simulation, the output reference voltage is 1.203 V with a temperature drift coefficient of 2.635 ppm/°C over the temperature range of −40°C to 125°C. The PSRR is −144.4 dB at a frequency of 10 Hz, and −43.8 dB at a frequency of 1 MHz, and the layout area is 316 μm × 156 μm.

Producer services agglomeration and low-carbon economic transition: the role of economic growth target constraint

Abstract Objective. Producer services are an intermediate input factor that permeates every link in the industrial production chain and is essential to the growth of a low-carbon economy. This study aims to elucidate the connection between producer services agglomeration (PSA) and low-carbon economic transition. Methods. Based on China’s provincial panel data from 2004 to 2021, we empirically test the influence of PSA on low-carbon economic transition using a two-way fixed effects model, and utilize government work reports to construct an indicator of economic growth target constraints and its characteristics to further explore its moderating effect. Results. PSA contributes to enhancing low-carbon economic transition. The heterogeneity test finds that PSA significantly helps low-carbon economic transition in the east and west regions, but not in the central region. The quantile regression findings demonstrate that PSA is more effective at raising the level of low-carbon economic transition at the 10th and 90th quantiles, which indicates that the carbon reduction and efficiency enhancement effects of PSA play a greater role in regions with lower and higher low-carbon economic transition levels. Further research presents that the economic growth target constraint negatively moderates PSA’s impact on low-carbon economic transition, but this constraint characterized by soft constraints strengthens the positive effect of PSA on low-carbon economic transition. Implications. In view of this, the government can foster PSA in accordance with local conditions, optimize agglomeration area layout, and establish a scientific and reasonable government target management system to strengthen low-carbon and high-quality economic development.

Threats and Membership of Kandovan in UNESCO

This research aims to explore the heritage and tourist zone of Kandovan in Iran, currently undergoing the UNESCO registration process, but facing rejection due to threats in the area. The primary goal is to offer valuable insights to the Kandovan municipality and officials, assisting them in recognizing and mitigating the prevailing threats to secure the designation of Kandovan as a UNESCO heritage site. The examination of the heritage zone in Kandovan, Iran, involved a comprehensive approach incorporating a literature review, interviews, and on-site observations. Interviews were conducted with Kandovan officials to inquire about the heritage criteria, existing challenges and threats, future initiatives, and notable transformations. Field observations were employed to assess the physical characteristics and layout of the heritage area, residents' interactions with the heritage sites, and issues affecting tourists, including accommodation shortages and architectural concerns. The findings of this study have identified the threats present in Kandovan, as acknowledged by UNESCO. The majority of these threats have emerged as a consequence of the expanding urbanization and tourism activities in Kandovan, emphasizing the need for effective management and controlled development in the area.

Design of a low-power Digital-to-Pulse Converter (DPC) for in-memory-computing applications

Data converters such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital-to-time converters (DTCs), time-to-digital converters (TDCs), among others, are considered some of the most essential blocks in the field of integrated circuit design. In this work, we introduce a novel type of data converter known as the Digital-to-Pulse converter (DPC) and present its novel analog flow circuit implementation. The DPC system is a critical component in emerging artificial neural network accelerators and in-memory computing systems. The DPC system presented in this study offers two distinct operating modes. The first mode is the generation of a single pulse with a width that is modulated by the digital input. The second mode is an n-bit digital to discrete pulse converter, where the number of generated pulses is directly related to the value of the digital input. The proposed DPC system offers designers a high level of flexibility in shaping the characteristics of the output pulses, including the number of pulses, pulse width, and pulse amplitude. This empowers designers to accommodate different application requirements and scenarios effectively. The proposed circuit has been verified and tested using Virtuoso Cadence circuit tools in 180 nm CMOS technology with post-layout simulation and analysis. The results indicate a significant enhancement in average power consumption (∼12×), layout area (∼5×), and latency (∼1.4×) with the proposed system compared to the digital Register Transfer Level (RTL) implementation under a power supply of 1.8V and a clock frequency of 1 GHz in the Application Specific Integrated Circuits (ASIC) flow. This demonstrates the suitability of the proposed system for low-power and high-speed applications.