Layout Level Research Articles

IJIREEICE - Electrical, Electronics, Instrumentation and Control

The use of the VHSIC Hardware Description Language (VHDL) has become very important to the simulation and implementation of digital systems in both industry and educational settings. Al-though VHDL is a powerful language with many capabilities, it has downfalls when considering the difficulty in learning the language as well as its limited capabilities for transitioning a design from initial concept to design entry and verification stages. This paper discusses techniques used to teach the VHDL design methodology to graduate students, as well as methods used to go through a complete design cycle from initial concept to final implementation. VHDL design techniques were developed using various projects and homework assignments, and different approaches to implementing the same function allowed direct comparisons of the speed and size of the designs. Different processes for taking a design from ini-tial concept through chip implementation were discussed, and one example of the process is discussed here. This paper describes the implementation of full adder using VHDL technology which meets less complexity requirement ,it also shows how efficiently digital system ie Full Adder is implemented upto layout level results shows technological map RTL view ,chip floor plan ,chip layout ,output waveforms showing voltage Vs time relations and verification of truth table .

Guest Editorial

Guest Editorial

Low‐level implementation and side‐channel detection of stealthy hardware trojans on field programmable gate arrays

Hardware Trojans (HTs) are an emerging threat for integrated circuits integrity and their applications. Trying to find efficient HT detection methods is necessary. However, before detecting them, HTs need to be created with an efficient method and their effects need to be understood. There are very few studies which describe HTs implementation methods and the methods used are not convenient for systematic study of HTs effects. The Trust-Hub website, known for hardware security in general, had published a full HT implementation tutorial, which is not completely satisfying. This study proposes a stealthy and reusable HT implementation method on field programmable gate arrays at the layout level adapted for the study of different HTs with the same non-infected circuit. Created for a systematic study of the effects brought by different HTs, the proposed approach allows designers to insert stealthy HTs inside the same circuit in order to create different realistic infected circuits. HTs implementation results on an advance encryption standard system and detection experiments based on side-channel are also presented in this study. The implementation method the authors propose can be used with scripts in order to accelerate the insertions of HTs variants.

Design of ternary clock generator

A ternary clock generator (TCG) is proposed to settle its shortage. The TCG is implemented at the switch level with a simple structure of 24 MOS transistors and simulated at the layout level using the HSPICE software with TSMC 0.18 μm CMOS technology, showing that it works properly. The analyses show that the proposed TCG not only can output a ternary clock of high quality, meeting the clock's design requirements, but also can be fabricated with standard CMOS technology.

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

A regular fabric design methodology for applications requiring specific layout-level design rules

Regular fabrics have been introduced as an approach to bridge the gap between ASICs and FPGAs in terms of cost and performance. Indeed, compared to an ASIC, by predefining most of the manufacturing masks, they highly reduce time-to-market, non-recoverable engineering costs and lithography hazards. Also, thanks to hardwired configuration and interconnections their performance is closer to those of ASICs than those of FPGAs. They are therefore well suited to many applications requiring low to medium volume applications or higher performance than those provided by FPGAs.In this paper, we evaluate the interest of using a regular fabric to reduce time and design cost significantly in applications involving specific transistor level design (radiative/spacial conditions, side-channel attacks, NMR environment, etc.). With this aim in view, after a broad state of the art overview with an emphasis on architectures and design flows, we develop our approach of a regular fabric designed to limit layout level design, ad-hoc tools and technological migration cost. Then, we evaluate its performance in a 65 nm process versus FPGA and standard cell based ASIC implementations. For sequential designs, our proposed solution is on average 2.5×slower and 2.3×bigger than a standard cell implantation, but also on average 13×faster than a FPGA.

상수관망의 에너지 평가기법에 관한 연구

The systematic analysis and evaluation of required energy in the processes of drinking water production and supply have attracted considerable interest considering the need to overcome electricity shortage and control greenhouse gas emissions. On the basis of a review of existing research results, a practical method is developed in this study for evaluating energy in water supply networks. The proposed method can be applied to real water supply systems. A model based on the proposed method is developed by combining the hydraulic analysis results that are obtained using the EPANET2 software with a mathematical energy model on the MATLAB platform. It is suggested that performance indicators can evaluate the inherent efficiency of water supply facilities as well as their operational efficiency depending on the pipeline layout, pipe condition, and leakage level. The developed model is validated by applying it to virtual and real water supply systems. It is expected that the management of electric power demand on the peak time of water supply and the planning of an energy-efficient water supply system can be effectively achieved by the optimal management of energy by the proposed method in this study.

The concurrent block layout problem

The interdependency of block layout and detail level work centre layout is discussed and used to motivate the problem of concurrent block layout planning. The concurrent perspective emphasises the simultaneous minimisation of materials handling cost between work centres and maximisation of activity relationships within work centres. The resultant bi-criteria problem is formulated and a series of test problems are generated. Simple Monte Carlo simulation is used to demonstrate how modelling tools applied to the traditional block layout problem could be adapted in the development of a new class of algorithms based on the concurrent perspective.

Self-Diagnosis of Malaria by Travelers and Expatriates: Assessment of Malaria Rapid Diagnostic Tests Available on the Internet

IntroductionIn the past malaria rapid diagnostic tests (RDTs) for self-diagnosis by travelers were considered suboptimal due to poor performance. Nowadays RDTs for self-diagnosis are marketed and available through the internet. The present study assessed RDT products marketed for self-diagnosis for diagnostic accuracy and quality of labeling, content and instructions for use (IFU).MethodsDiagnostic accuracy of eight RDT products was assessed with a panel of stored whole blood samples comprising the four Plasmodium species (n = 90) as well as Plasmodium negative samples (n = 10). IFUs were assessed for quality of description of procedure and interpretation and for lay-out and readability level. Errors in packaging and content were recorded.ResultsTwo products gave false-positive test lines in 70% and 80% of Plasmodium negative samples, precluding their use. Of the remaining products, 4/6 had good to excellent sensitivity for the diagnosis of Plasmodium falciparum (98.2%–100.0%) and Plasmodium vivax (93.3%–100.0%). Sensitivity for Plasmodium ovale and Plasmodium malariae diagnosis was poor (6.7%–80.0%). All but one product yielded false-positive test lines after reading beyond the recommended reading time. Problems with labeling (not specifying target antigens (n = 3), and content (desiccant with no humidity indicator (n = 6)) were observed. IFUs had major shortcomings in description of test procedure and interpretation, poor readability and lay-out and user-unfriendly typography. Strategic issues (e.g. the need for repeat testing and reasons for false-negative tests) were not addressed in any of the IFUs.ConclusionDiagnostic accuracy of RDTs for self-diagnosis was variable, with only 4/8 RDT products being reliable for the diagnosis of P. falciparum and P. vivax, and none for P. ovale and P. malariae. RDTs for self-diagnosis need improvements in IFUs (content and user-friendliness), labeling and content before they can be considered for self-diagnosis by the traveler.

SLIDER: Simulation of Layout-Injected Defects for Electrical Responses

Logic-level simulation has been the de facto method for simulating defect/faulty behavior for various testing tasks since it offers a good tradeoff between accuracy and speed. Unfortunately, by abstracting defect behavior to the logic level (i.e., a fault model), it also discards important information that inevitably results in inaccuracies. This paper describes a fast and accurate defect simulation framework called SLIDER (simulation of layout-injected defects for electrical responses). SLIDER uses well-developed mixed-signal simulation technology that is conventionally used for design verification. There are three innovative aspects that distinguish SLIDER from prior work in this area: 1) accuracy resulting from defect injection taking place at the layout level; 2) speedup resulting from careful and automatic partitioning of the circuit into maximal digital and minimal analog domains for mixed-signal simulation; and 3) complete automation that includes defect generation, defect injection, design partitioning, netlist extraction, mixed-signal simulation, and test-data extraction. The virtual failure data created by SLIDER is useful in a variety of settings that include diagnosis resolution improvement, defect localization, fault model evaluation, and evaluation of yield/test learning techniques that are based on failure data analysis.

Design of an interactive digital nutritional education package for elderly people

Designing a system for the elderly is crucial, as aging is associated with physiological changes that may impair perception, cognition and other social aspects; therefore, many aspects need consideration, especially in interface design. This study was conducted to develop a digital nutritional education package (WE Sihat) by following appropriate guidelines for elderly people to achieve better design interface and interaction. Touch-screen technology was used as a platform for user interaction. The nutritional content was based on previous nutrition studies and a lifestyle education package on healthy aging, which contains four modules. The questionnaires were distributed to 31 Malay subjects aged 60–76 years old, containing an evaluation about the overall content, graphics, design layout, colour, font size, audio/video, user-perceived satisfaction and acceptance levels. The findings showed positive feedback and acceptance. Most subjects agreed that the digital nutritional education package can increase their nutritional knowledge for a healthy lifestyle and is easy to use. The touch-screen technology was also well accepted by elderly people and can be used as a kiosk for disseminating nutrition education for healthy aging.

OPTIMIZED IMAGE RETRIEVAL SYSTEM USING MULTIPLE THREADS

Content-Based Image Retrieval is a technique used to retrieve similar images where the most challenging aspect is to bridge the gap between low level feature layout and high level semantic concepts. Efficient and effective retrieval techniques of images are desired to work out a certain image on the condition that the result would be more suitable than the input image. A novel method is proposed, which links various images as threads; where the texture features and shape features of the images are extracted and stored. The minimum distance between the query image and the thread provides the output. These threads are based upon the query result. The resultant retrieval system is found to be beneficial and interactive.

Design of Oscillator for PWM Controller

An oscillator is designed for PWM controller chip. The resistance Rt and capacitance Ct for oscillator are located outside the chip to adjust the frequency expediently. The circuit is simulated by CADENCE Spectre, and the simulation results show that the frequency of the oscillator is 52.84KHz (at Vcc=15V), voltage stability is 0.4%. The layout is done based on the process flow and layout levels of bipolar 45V process provided by HUAYUE Microelectronics Company. The test results prove that the oscillator present in this paper meets the design requirements.

Design, Analysis and Simulation of High Performance Low Power 8-Bit ALU at Gate and Layout Levels

In this work, the demand is to design an 8-bit ALU and perform analysis at gate and layout levels. The design makes use of n-Bit slice concept, the requirement is to design and develop low power high performance circuits. To achieve this, the design requires advanced styles to be employed. High level description language to be used to construct layout of 8-bit ALU and then different analyses will be carried out on this layout. Keywords - ALU, Bit Slice, Low Leakage, Threshold Volatge. I. INTRODUCTION An Arithmetic and Logic Unit (ALU) is a digital circuit that performs arithmetic and logic operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs, a single component may contain a number of ALUs. The ALU at one machine cycle executes a number of operations. During the process of operations it consumes a lot of power. Due to the power consumed by the ALU has a direct impact in the power dissipated from the processor. Hence, a design is required to implement the ALU in a fashion where the performance of the processor is improved and also the power consumed is less. This paper provides a simple design of a 8 Bit ALU for a speedy performance. This paper introduces a technique to design a ALU which consumes less power. Bit slice design is used for the construction of the 8-Bit ALU.

Modelling and solution approaches to the multi-load AGV dispatching problem in container terminals

We consider the automated guided vehicle (AGV) dispatching problem in container terminals where vehicles are allowed to carry more than one container at a time. The main focus of the study is on dual-load AGVs, which may carry either two 20-ft containers or one 40/45-ft container. We propose a new mathematical formulation for the corresponding optimisation problem under a rolling horizon approach; the proposed model is a simplification over existing formulations. The performance of the model is evaluated against different scenarios with respect to minimising a defined dispatching ‘cost’. Our computational results are based on a number of scenarios for container terminals, with various layout configurations and levels of workload, and show that the model can generally be solved quickly providing good quality solutions.

DC-DC converters with reduced mass for trackers at the HL-LHC

The development at CERN of low noise DC-DC converters for the powering of front-end systems enables the implementation of efficient powering schemes for the physics experiments at the HL-LHC. Recent tests made on the ATLAS short strip tracker modules confirm the full electromagnetic compatibility of the DC-DC converter prototypes with front-end detectors. The integration of the converters in the trackers front-ends needs to address also the material budget constraints. The impact of the DC-DC converters onto the material budget of the ATLAS tracker modules is discussed and mass reduction techniques are explored, leading to a compromise between electromagnetic compatibility and mass. Low mass shield implementations and Aluminum core inductors are proposed. Also, the impact on emitted noise due to a size reduction of critical components is discussed. Finally, material reduction techniques are discussed at the board layout and manufacturing levels.

A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

In this paper, we propose a simulation-before-test (SBT) fault diagnosis methodology based on the use of a fault dictionary approach. This technique allows the detection and localization of the most likely defects of open-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS) analog integrated circuits (ICs) interconnects. The fault dictionary is built by simulating the most likely defects causing the faults to be detected at the layout level. Then, for each injected fault, the spectre’s frequency responses and the power consumption obtained by simulation are stored in a table which constitutes the fault dictionary. In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate a considered defect. When testing, the circuit under test is excited with the same stimulus, and the responses obtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full custom CMOS operational amplifier is implemented in 0.25 µm technology and the most likely faults of opencircuit type are deliberately injected and simulated at the layout level.

Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits

The rate of soft errors have been significantly increasing due to the aggressive scaling trends in the nanometer regime. Several circuit optimization techniques have been proposed in literature for preventing such transient faults, however, to the best of our knowledge, the reduction of soft error rate at the layout level has not been attempted in logic circuits. In this work, we show that transient glitches due to cosmic strikes can be sufficiently reduced by intelligently modifying the placement stage in cell based designs to selectively assign larger wirelengths to certain critical nets. Towards this, we propose a computationally efficient placement algorithm based on quadratic programming that significantly reduces the soft error rates of logic circuits. The algorithm tries to assign higher wirelengths for nets with low glitch masking probabilities for higher reduction in soft error rates (SER), while maintaining low delay and area penalty for the overall circuit. Experimental results on the ISCAS'85 benchmark circuits indicate that such a placement algorithm can significantly improve the soft error immunity in logic circuits without much delay and area overheads.

Design and simulation of a flexible beamforming interface for MIMO receivers using a Butler labyrinth

This article focuses on the design and simulation of a new component for analog beamforming based on the Butler labyrinth. The proposed component enables the analysis of four-antenna beamforming in systems with two receive channels. The problem was to design a component that would enable simulation of a MIMO receiver with an accurate account of the analog beam-former effects on the digital signal processing level. The entire process is described—from layout design to the final DSP level integration and simulation. The performance of the simulated Butler component is compared to that of an ideal, theoretical one. The differences in the results indicate the importance of taking into account the effects of the layout level design on the DSP simulation level. The new component proves valuable for the bottom-up approach in the design and simulation of a wireless system. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.

Climate responsive approach to architecture design

This paper is an attempt to document an experimental approach to studio design project at level 3 of architecture education. Experiential learning, especially at lower levels, helps in analysing, synthesising, and evaluating the design scientifically and logically. The studio project is of ‘multiple dwelling’ and the thrust is on the climatic sensitivity. Sun and wind studies have been carried out at unit, cluster and layout levels. This studio exercise aimed at generating a stimulus amongst pupils for the climatic issues and integration of climatology as a subject into the design studio. Sundial and the wind stimulator have been the tools used for arriving at design decisions.