Layout Design Method Research Articles

A macrocell approach for VLSI processor design

An effective layout design method for VLSI processors, called the 'macrocell approach' is presented. The approach bridges the gap between full manual layout and polycell/standard cell layout with respect to the design productivity and the performance. After precise floorplanning, functional blocks are designed into macrocells using a flexible symbolic layout method, and a VLSI chip is laid out by an automatic layout program. A 16-bit digital signal processor (DSP) was designed using 2- mu m CMOS technology. Both high packing density of 1150 transistors/mm/sup 2/ and high productivity of 6.5 transistors/day for symbolic layout were attained in the design. After fabrication, the chip operated with the first silicon, realizing high-speed operation in an application program for a 32-kb/s ADPCM CODEC (adaptive differential pulse-code modulated coder-decoder). >

Compaction-Based Custom LSI Layout Design Method

This paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1.2-1.4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design.