Lateral Double-diffused Metal Oxide Research Articles

A novel SOI-LDMOS with field plate auxiliary doping layer that has improved breakdown voltage

Field plate (FP) is a widely used electric field optimization technique in lateral power devices. However, we found that the electric field distribution optimized by FP still has poor uniformity due to the excessive induced charges at the end of FP. To solve the problem, a novel silicon on insulator based lateral double diffused metal oxide semiconductor (SOI-LDMOS) with a field plate auxiliary doping layer (FPADL) is proposed. Our investigation proved that the FPADL introduces an additional part of space charge and partially balances the excessive induced charges at the end of FP. As a result, the FPADL introduces an additional electric field peak and improves the electric field distribution. Thereby, the SOI-LDMOS with FPADL has improved breakdown voltage (BV). The effect of FPADL is verified experimentally. In our experiment, the FPADL is realized by modifying the mask of buffer layer to avoid increasing the process cost. The measurement results showed that, comparing with the conventional SOI-LDMOS with FP, the proposed SOI-LDMOS with FPADL improved the BV by 9.52% with the on-resistance and the process cost maintained. Therefore, the proposed SOI-LDMOS with FPADL is a promising device.

Design considerations of a novel Triple Oxide Trench Deep Gate LDMOS to improve self‐heating effect and breakdown voltage

In this study, design considerations of a new device structure are presented to improve the self-heating effect (SHE) and the breakdown voltage of the Deep Gate LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) transistor and compared with a conventional LDMOS (C-LDMOS). In this case, triple oxide trenches with an N+ trench are embedded in the drift region. These trenches create additional peaks in the electric field profile, so the electric field is modified. The authors demonstrate that by optimising the trenches, the breakdown voltage of the device increases. Also, a partially buried oxide is used in the proposed structure to create a conduction path that significantly reduces the SHE. Moreover, the results indicate that the specific on-resistance, lattice temperature, and breakdown voltage of the proposed device are improved considerably compared to the C-LDMOS.

Deep neural network-based approach for breakdown voltage and specific on-resistance prediction of SOI LDMOS with field plate

Breakdown voltage (BV) and specific on-resistance (R on,sp), are critical indicators to measure the quality of the power device. To improve the device performance, field plate technology has been developed by modifying the electric field distribution. However, the current technology computer-aided design (TCAD) simulation cannot predict the effect of field plate on BV and R on,sp simultaneously, and the operation process is complicated. This paper proposes a deep neural network (DNN)-based model instead of TCAD to predict the effect of field plates on BV and R on,sp of silicon on insulator lateral double diffused metal oxide semiconductor. The experimental results show that, compared with TCAD simulation, the average deviation for BV and R on,sp is 5.06% and 2.55%, respectively. Also, the time for BV prediction is accelerated significantly up by 1.23 × 105. Our DNN model provides a potential direction to predict device performance with higher efficiency.

A Ultra-Low Specific On-Resistance and Extended Gate SJ LDMOS Structure

A new structure of extended gate (EG) SJ LDMOS is proposed in this paper to overcome the substrate assisted depletion (SAD) effect in the structure of Super-Junction lateral double diffused metal oxide semiconductor (SJ LDMOS). Different from other surface SJ structures, the SJ layer of the structure is located in the body of the drift region. Gate oxide and silicon layer form the EG Structure-Oxide-Semiconductor structure that is similar to Metal–Insulator–Semiconductor capacitor. The the N-drift of the EG structure can obtain the charge compensation to overcome the SAD effect, and a nearly rectangular electric field is achieved. In the on-state, the EG structure has two conductive channels and the accumulation layer is formed on the drift region. By accumulating high concentration electrons in the channels, the specific on-resistance (RON,sp) is greatly reduced. When the drift length is 24 μm, 431.4 V breakdown voltage (VB) and 9.8 mΩ cm2 RON,sp are achieved, and the figure of merit is 18.9 MW cm−2.

Improved Model on Buried-Oxide Damage Induced by Total-Ionizing-Dose Effect for HV SOI LDMOS

In this article, an improved model on buried-oxide (BOX) damage induced by total-ionizing-dose (TID) effect considering positive oxide trapped charge ( N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> ) generated in silicon on insulator (SOI)/BOX interface under negative electric field bias (field lines perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX) and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> saturation effect is proposed and adopted in accurate simulated analysis to predict the postirradiation device behavior. Moreover, the mechanism of high-voltage (HV) SOI lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) degradation during irradiation is also revealed by the proposed accurate simulation method. Tolerance design for radiation-hardened HV SOI LDMOS is discussed with the aid of the presented model. The tradeoff between postirradiation electrical characteristics and fresh electrical characteristics should be taken into account to meet the radiation hardening requirement. The radiation-hardened-by-design LDMOS introduced in this article keeps an OFF-state breakdown voltage above 120 V at D = 500 krad(Si) with operating voltage equal to 80 V, which is fabricated on a commercial SOI substrate material with plain interface quality parameters. The corresponding hardening strategy is also given.

A Novel Deep Gate LDMOS Structure Using Double P-Trench to Improve the Breakdown Voltage and the On-State Resistance

To increase the breakdown voltage and reduce the on-state resistance, a novel Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) field-effect transistor is proposed in this paper. In the proposed structure, double P-trenches are inserted in the buried oxide under the source and drain regions. The proposed device is called as the double p-trench deep gate LDMOS (DPTDG-LDMOS). By optimizing the P-trenches, the electric field will be more uniform, and so the maximum breakdown voltage obtains. Our simulation results show that the breakdown voltage, on-state resistance, maximum temperature (TMAX), and figure of merit (FOM) for the DPTDG-LDMOS are improved in comparison with a conventional LDMOS.

The New Structure and Analytical Model of a High-Voltage Interconnection Shielding Structure With High-k Dielectric Pillar

The high-voltage interconnection (HVI) effect induces electric field crowding near the source region of power lateral double diffused metal oxide semiconductor field effect transistors (LDMOSs) and, therefore, weakens its breakdown voltage (BV) characteristic. To suppress such a detrimental effect, a novel HVI structure with a high- ${k}$ dielectric pillar beneath the HVI metal line is proposed. An analytical model is proposed to reveal the mechanism of the proposed structure and explain the effects of the parameters of the structure. The analytical model indicates that the high- ${k}$ dielectric pillar eliminates the electric field crowding near the source, promotes the depletion of the drift region, and avoids the premature breakdown. Meanwhile, due to the existence of the high- ${k}$ dielectric pillar, the surface electric field profile in the drift region can be modulated, and the influence of HVI can be effectively suppressed. Thus, a higher BV is obtained. The simulation results indicate that the proposed structure presents better BV, which is the same as that of the reduced surface field (RESURF) structure without HVI.

Optimization and Experiments of Lateral Semi-Superjunction Device Based on Normalized Current-Carrying Capability

A lateral double diffused metal oxide semiconductor transistor with the semi-superjunction (semi-SJ LDMOS) is optimized based on the normalized current-carrying capability (CC) and experimentally realized in this letter. The device is fabricated based on an optimized equivalent substrate and the semi-SJ is introduced near the source. The semi-SJ increases the local doping concentration in the N regions meanwhile reduces the current path area and carrier mobility, resulting in the variation of CCs before and after the introduction of the semi-SJ. The normalized CC factor $\eta _{\text {C}}$ is proposed to evaluate this variation, with which the minimum specific on-resistance ${R} _ {\text {ON}, \text {sp}}$ is predicted by the condition of $\eta _{\text {C}}= {1}$ . The experiments of the semi-SJ LDMOS exhibit a minimum ${R} _ {\text {ON}, \text {sp}}$ of 25.5 $\text{m}\Omega \cdot $ cm2 under a breakdown voltage ${V} _{{\text {B}}}$ of 464.3 V. This represents a reduction in ${R} _ {\text {ON}, \text {sp}}$ by 37.7% when compared with the theoretical ${R} _ {\text {ON}, \text {sp}}$ of triple RESURF devices.

A Novel High Voltage Ultra-Thin SOI-LDMOS With Sectional Linearly Doped Drift Region

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a 0.17 μm SOI layer with a source field plate covering the full drift region. Low specific on-resistance Ron,sp is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> of 960 V with a superior figure of merit (FOM = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) of 5.98 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.

A New Structure for Lateral Double Diffused MOSFET to Control the Breakdown Voltage and the On-Resistance

Lateral Double Diffused Metal Oxide Field Effect Transistor (LDMOS) are widely used in power applications for the high breakdown voltage. However, the device may have high on-resistance. So, the challenge for achieving high breakdown voltage and small on-resistance is important. In this paper, a new structure is proposed to enhance the conventional LDMOS performance. In this case, a U-shape P silicon layer is considered in bottom of the drift region and under the gate. The P layer has higher doping density than the drift region which is different from the channel and source/drain. This difference creates some new peaks in the electric field profile decreasing the main peaks. Therefore, the breakdown voltage significantly increases. The on-resistance is reduced when the doping density increases. The higher doping density of P layer than drift region reduces the on-resistance. The paper is simulated using two dimensional ATLAS simulator and is compared to the conventional one. The simulation results show that the proposed structure performance is acceptable in case of electric voltage, breakdown voltage, on-resistance and switching characteristics.

Double trenches LDMOS with trapezoidal gate

A novel double trenches lateral double diffused metal oxide semiconductor with trapezoidal gate (TGDT LDMOS) is proposed. One feature of the device is that two dielectric trenches which are equivalent to two field plates are introduced in the drift region. The two dielectric trenches not only modulate the body electric field to improve the breakdown voltage (BV) of the device but also assist to deplete the drift region to reduce the specific on-resistance ( R on,sp ). The other feature is the presence of the trapezoidal gate which increases the gate oxide thickness to reduce the capacitance of gate and drain ( C GD ). Thereby the charge between the gate and drain ( Q GD ) is reduced, so that the conduction loss of the device is decreased. Compared with the conventional LDMOS with trapezoidal gate and the single trench LDMOS with trapezoidal gate, the figure of merit (FOM = BV 2 / R on,sp ) of the TGDT LDMOS is increased by 112.5 and 54.5%, respectively. Compared with the conventional double trenches LDMOS with rectangle gate, the FOM is similar, but the Q GD is reduced by 45.7%. Simultaneously, the feasible process steps of the TGDT LDMOS are given in this work.

Modeling of Breakdown Voltage for SOI Trench LDMOS Device Based on Conformal Mapping

An analytical model is proposed in this paper to predict the breakdown voltage (BV) of silicon-on-insulator (SOI) trench lateral double diffused metal oxide semiconductor (LDMOS) devices with N/P pillars. In this SOI trench LDMOS device, the U-shaped folded drift region is divided into four parts for simplifying the solution of Poisson's equation, where conformal mapping by the Schwarz-Christoffel (S-C) transformation is applied. As verified by the TCAD simulation results, the analytical model may predict the electric field distribution and the BV accurately. This analytical model can reveal the essence of the electric field peaks around the dielectric trench from the depletion effect of the N/P pillars.

The Simulation Study of the SOI Trench LDMOS With Lateral Super Junction

A novel lateral double diffused metal oxide semiconductor (LDMOS) with trench oxide layer, featuring a lateral super junction structure based on the silicon-on-insulator technology is proposed. On the one hand, the lateral super junction combined with the TOL can enhance both the surface and the bulk electric field of the N-drift by the charge compensation. Thus, the breakdown voltage (BV) is improved. On the other hand, the N-Pillar of the lateral super junction provides another current channel for electrons at the forward conduction state, thus the Specific on resistance ( $\text{R}_{\mathrm{on,sp}}$ ) is decreased. As the simulation results show, the proposed LDMOS exhibits trapezoidal electric field distribution with BV of 422V, and double electron channels with $\text{R}_{\mathrm{on,sp}}$ of 30.7 $\text{m}\Omega \cdot $ cm2, thus the figure of merit (FOM) (FOM = BV2/ $\text{R}_{\mathrm{on,sp}}$ , Baliga’s FOM) of 5.82 MW/cm2 is achieved, breaking through the silicon limit.

New folding lateral double diffused metal oxide semiconductor breaking silicon limit with ultra‐low specific on‐resistance

A new lateral double diffused metal oxide semiconductor (LDMOS) is proposed for the first time with the step oxide layer above the folding silicon substrate. Three technologies, including of the electric field modulation effect, majority carrier accumulation, and folding silicon, are applied simultaneously to the proposed LDMOS for improving the trade-off between the breakdown voltage (BV) and specific on-resistance (R on,sp). The majority carrier accumulation layer under the extended gate is formed in the folding silicon substrate during the on-state operation. The high-doping drift region can be depleted completely in the off-state, thanks to an additional electric field modulation, which is analogous to the super junction idea. The uniform lateral electric field has been obtained due to the new electric field peak to improve the trade-off between the BV and R on,sp. The proposed LDMOS shows the R on,sp of 0.32 mΩ cm2 with the BV of 62 V, which has broken the silicon limit relationship with R on,sp of 2.0 mΩ cm2 under the same BV in the conventional LDMOS. This is the previously reported lowest R on,sp with the BV of about 60 V.

A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs.Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100μA), at drain–source voltage of VDS=100V and gate–source voltage of VGS=25V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87μA and 51μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors

In this paper a new lateral double diffused metal oxide semiconductor (LDMOS) transistor on silicon-on-insulator (SOI) technology is reported. In the proposed structure a trench oxide in the drift region is reformed to reduce surface temperature. In the LDMOS devices one way for achieving high breakdown voltage is incorporating the trench oxide in the drift region. But, this strategy causes high lattice temperature in the device. So, the middle of the trench oxide in the drift region is etched and filled with the silicon to have higher thermal conductivity material and reduce the lattice temperature in the drift region. The simulation with two-dimensional ATLAS simulator shows that the novel thin trench oxide in the n-drift region of LDMOS transistor (TT-LDMOS) have lower maximum lattice temperature with an acceptable breakdown voltage in respect to the conventional LDMOS (C-LDMOS) structure with the trench oxide in the drift region. So, TT-LDMOS can be a reliable device for power transistors.

An area-efficient LDMOS-SCR ESD protection device for the I/O of power IC application

Lateral Double diffused Metal Oxide Semiconductor (LDMOS) transistors are widely used in HV output circuit and its Electrostatic Discharge (ESD) problem have been well studied. LDMOS embed Silicon Controlled Rectifier (LDMOS-SCR) can be used to improve LDMOS ESD robustness. In order to further enhance the ESD self-protection capability of LDMOS-SCR, a new device LDMOS-SCR with a floating P+implant region (FP-LDMOS-SCR) is proposed in this paper. Due to the floating P+implant region is placed near the drain end, It2 of the new FP-LDMOS-SCR device increases obviously, compared with traditional LDMOS and LDMOS-SCR devices. The FP-LDMOS-SCR′s It2 with one floating P+is 1.3A and that with two floating P+is 2.7A. The results of Technology Computer Aided Design (TCAD) simulations will be presented in this paper to help analysis the physical mechanism and observe the ESD behavior of the LDMOS-SCR. The proposed FP-LDMOS-SCR, same driver capability with LDMOS, can be applied in HV output circuit and also provide its ESD self-protection through shunted ESD stress to ground.

A low on-resistance silicon on insulator lateral double diffused metal oxide semiconductor device with a vertical drain field plate

To reduce the on-resistance and enhance the breakdown voltage of silicon on insulator (SOI) lateral double diffused metal oxide semiconductor (LDMOS) device at the same time, a low on-resistance SOI-LDMOS device with a vertical drain field plate and trench gate and trench drain (VFP-TGTD-SOI-LDMOS) is proposed. The device has the features as follows: first, a trench gate and a trench drain are adopted, which can widen the vertical current conduction area, shorten the lateral current conduction path, and lower the on-resistance. Secondly, a vertical field plate is used, which modulates the electric field around it, reduces the high electric field at the end of the drain electrode, and increases the breakdown voltage. The VFP-TGTD-SOI device is compared with a conventional SOI device, a trench gate SOI device, a trench gate and trench drain SOI device with the same dimensional device parameters using the two-dimensional semiconductor simulator MEDICI. The results show that under the condition of their own highest figure of merit (FOM), the specific on-resistance value of the VFP-TGTD-SOI device is reduced by 53%, 23%, and increased by 87%, respectively and the breakdown voltage is increased by 4% and reduced by 9% and increased by 45%, respectively. By comparing the FOMs of the four structures, it can be seen that the VFP-TGTD-SOI device has the highest FOM, which indicates that among the four structures, it maintains the lower on-resistance and holds the higher breakdown voltage at the same time.

A novel partial-SOI LDMOSFET (>800 V) with n-type floating buried layer in substrate

In this paper, a novel high voltage lateral double diffused metal–oxide–semiconductor (LDMOS) field effect transistor based on partial silicon-on-insulator (PSOI) technology is proposed and investigated based on the numerical simulations. The structure is characterized by an n-type floating buried layer (NFBL) in the substrate under the silicon window near the drain. The buried layer in the substrate modulates the lateral and vertical electric field, which results in the electric field of the drift region distributed uniformly. Therefore, the breakdown voltage (BV) of the device is significantly improved. The influences of the key parameters on device performance of the proposed structure are discussed. Moreover, the self-heating effect (SHE) is greatly alleviated duo to the silicon window helps thermal conduction to the substrate, which improved the reliability of device application.

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.