Latent Interface-trap Buildup Research Articles

Aging Effects and Latent Interface-Trap Buildup in MOS Transistors

Effects of ~35 years of aging during storage are investigated on the radiation response and 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f$ </tex-math></inline-formula> noise of Oki nMOS and pMOS transistors with high oxygen vacancy densities in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Short-term interface-trap buildup during irradiation is enhanced significantly, relative to that observed in 1989, 1997, and 2008. In contrast, a similar latent interface-trap buildup is observed for aged pMOS devices irradiated and annealed at room and elevated temperatures at positive bias in this and earlier studies. The significant latent interface-trap buildup is observed for nMOS devices irradiated at 0 V and annealed at room and elevated temperatures under positive bias, a condition not evaluated in prior work. Results strongly suggest that latent interface-trap buildup is due to H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> diffusion and dissociation at charged or dipolar O vacancies in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , followed by proton transport to the Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface and reactions with Si–H complexes. Models that attribute latent interface-trap buildup to long-term proton trapping at O vacancies in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> appear to be ruled out by these results. Additional insight is provided into mechanisms of postirradiation interface- and border-trap buildup after long-term MOS device storage.

Defect Interactions of ${\hbox{H}}_{2}$ in ${\hbox{SiO}}_{2}$: Implications for ELDRS and Latent Interface Trap Buildup

The energetics of the interactions between molecular hydrogen and common defects in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> that are typically associated with O deficiency have been obtained using atomic-scale quantum mechanical calculations. H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> does not easily crack at neutral vacancies, but it will crack efficiently at O vacancy sites that have captured a hole and relaxed into the puckered configuration of an E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">γ</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">'</sup> defect, releasing a proton into the oxide. Isolated Si dangling bonds also can play a role in cracking H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , depending on their concentration in the oxides. These results provide significant insight into the underlying causes of latent interface trap buildup in MOS devices and enhanced low-dose-rate sensitivity in linear bipolar devices.

Total ionizing dose effects and annealing behavior for domestic VDMOS devices

Total dose effects and annealing behavior of domestic n-channel VDMOS devices under different bias conditions were investigated. The dependences of typical electrical parameters such as threshold voltage, breakdown voltage, leakage current, and on-state resistance upon total dose were discussed. We also observed the relationships between these parameters and annealing time. The experiment results show that: the threshold voltage negatively shifts with the increasing of total dose and continues to decrease at the beginning of 100 °C annealing; the breakdown voltage under the drain bias voltage has passed through the pre-irradiation threshold voltage during annealing behaving with a “rebound" effect; there is a latent interface-trap buildup (LITB) phenomenon in the VDMOS devices; the leakage current is suppressed; and on-state resistance is almost kept constant during irradiation and annealing. Our experiment results are meaningful and important for further improvements in the design and processing.

Properties of latent interface-trap buildup in irradiated metal–oxide–semiconductor transistors determined by switched bias isothermal annealing experiments

Isothermal annealing experiments with switched gate bias have been performed to determine the properties of the latent interface-trap buildup during postirradiation annealing of metal–oxide–semiconductor transistors. It has been found that a bias-independent process occurs until the start of the latent interface-trap buildup. During the buildup itself, oxide-trap charge is not permanently neutralized, but is temporarily compensated.

New experimental evidence of latent interface-trap buildup in power VDMOSFETs

The paper presents new experimental evidence of the latent interface-trap buildup during annealing of gamma-ray irradiated power VDMOSFETs. We try to reveal the nature of this still ill-understood phenomenon by isothermal annealing, switching temperature annealing and switching bias annealing experiments. Possible explanations of obtained experimental results are discussed in the context of several models for post-irradiation behavior of radiation-induced defects.

Analysis of postirradiation annealing of n-channel power vertical double-diffused metal–oxide–semiconductor transistors

The behavior of densities of the oxide trapped charge and the interface traps in gamma-ray irradiated n-channel power vertical double-diffused metal–oxide–semiconductor transistors during annealing at different temperatures and gate biases has been investigated. The experimental results have revealed the existence of a latent interface trap buildup (LITB) process. By use of numerical modeling, based on the hydrogen–water (H–W) model, the LITB process has been successfully simulated. The interface trap densities have been determined by both the midgap and the charge pumping methods, and the results have shown good qualitative agreement between these two methods. Isochronal annealing and switching bias experiments have also been performed. The experimental results are consistent with the H–W model.

Numerical simulation of creation-passivation kinetics of interface traps in irradiated n-channel power VDMOSFETs during thermal annealing with various gate biases

Influence of gate bias on creation-passivation processes of interface traps in irradiated n-channel MOS transistors during thermal annealing has been investigated. The experimental results, which show the dependence of these processes on gate bias, are explained by combined hydrogen-water (H-W) model. The modelling of kinetics of creation and passivation of interface traps, based on bimolecular theory and numerical analysis, is also performed. Numerical simulation shows that H-W model predicts the maximum of interface trap density and latent interface trap buildup during thermal annealing.

Latent interface-trap generation in commercial power VDMOSFETs

Latent interface-trap generation is one of the most controversial post-irradiation effects in MOSFETs, which can have a significant impact on device performance and reliability in radiation environments. In this paper, we present new experimental evidence of latent interface-trap buildup in commercial power VDMOSFETs: its dependencies on dose, temperature and gate bias applied during irradiation and annealing. We discuss several models for latent interface-trap buildup and show that the most consistent is one which involves the diffusion of molecular hydrogen from structures adjacent to the gate oxide (CVD oxide, poly-Si gate), and its cracking on positive charge centers in the oxide. The cracking reaction liberates hydrogen ions, which drift to the Si/SiO/sub 2/ interface to form interface traps. Some hypothesis from the recently proposed H-W model for post-irradiation behavior of interface traps may help resolve the question of the source of hydrogen sufficient to cause up to 800% increase in interface-trap density, experimentally observed. The implications of latent interface-trap generation for hardness assurance test methods are also discussed.

Modelling of kinetics of creation and passivation of interface traps in metal-oxide-semiconductor transistors during postirradiation annealing

The dependencies of creation–passivation processes of interface traps in irradiated n-channel metal-oxide-semiconductor transistors on the temperature and gate bias during annealing have been investigated. The experimental results, which are explained by the hydrogen–water (H–W) model, show the influence of both the annealing temperature and gate bias on these processes. The modelling of creation–passivation kinetics of interface traps, based on bimolecular theory and numerical analysis, is also performed. Numerical modelling shows that the H–W model can include the temperature and gate bias dependencies of creation of interface traps, latent interface trap buildup and the decrease of interface trap density.

1/f noise, hydrogen transport, and latent interface-trap buildup in irradiated MOS devices

A large, delayed increase is observed in the postirradiation 1/f noise of Oki pMOS transistors prior to the onset of latent interface-trap buildup. Both effects are evidently due to similar thermally activated processes involving hydrogen. The increased noise through irradiation and anneal is found to be caused not only by the generation of defects at or near the Si/SiO/sub 2/ interface, but also by an apparent transition from buried to surface channel conduction. This is evidently triggered by the passivation of dopants in the Si by hydrogen transport during irradiation and anneal. Switched bias annealing confirms many of these effects are reversible. Three types of hydrogen transport are identified in MOS oxides: dispersive transport leading to two-stage interface-trap buildup, retarded transport leading to latent interface-trap buildup, and blockaded transport leading to proton confinement in SiO/sub 2/. The nature of the transport appears to correlate with O vacancy density and the temperature at which hydrogen is incorporated into the SiO/sub 2/. Implications are discussed for enhanced bipolar low dose rate response, the sensitivity of pMOS dosimeters, and protonic nonvolatile memory elements.

Correlation between latent interface trap buildup and 1/f noise in metal–oxide–semiconductor transistors

A long-term delayed increase in the 1/f noise of p-channel metal–oxide–semiconductor (MOS) transistors is observed in devices that show significant latent interface-trap buildup after exposure to ionizing radiation. During positive-bias postirradiation anneal, the noise increases by more than an order of magnitude above the level observed after irradiation. The increase in noise precedes the latent buildup of interface traps by at least 4.5 days during room-temperature annealing, and by ∼1 h during 100 °C annealing. The time and temperature dependencies of the increases in noise and interface trap buildup are consistent with the thermally activated motion of protons into the near-interfacial region of the oxide, followed by increases in border trap and interface trap densities. These results suggest hydrogen-related species can significantly affect the 1/f noise of MOS devices.

Latent interface-trap buildup and its implications for hardness assurance (MOS transistors)

Long-term anneals at temperatures from 25 degrees C to 135 degrees C were performed on irradiated MOS transistors. Following the normal saturation of interface-trap density (within 10/sup 2/ to 10/sup 5/ s after irradiation), large increases in the number of interface traps were observed for both commercial and radiation-hardened transistors at very long times after irradiation (>10/sup 6/ s at 25 degrees ). This latent buildup of interface traps can be significant, up to a factor of four times larger than the normal saturation value. The latent buildup is thermally activated with an activation energy of 0.47+or-0.08 eV. As a natural consequence of the delay between the normal and the latent buildup, there is a window in time in which little or no interface-trap buildup occurs. Two possible mechanisms for the latent buildup are explored: (1) the direct conversion of oxide traps into interface traps or border traps and (2) the diffusion of molecular hydrogen into the gate oxide from adjacent structures. The latent buildup of interface traps can degrade the performance of ICs in space systems and may cause IC failure at long times. Recommendations are provided for characterizing latent interface-trap buildup.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Latent thermally activated interface-trap generation in MOS devices

A large increase in interface-trap density (up to a factor of five) has been observed in commercial MOS devices at very long times after irradiation (>10/sup 6/ s). This latent buildup occurs after an initial apparent saturation of interface-trap density, which occurs typically within approximately 10/sup 2/-10/sup 4/ s after irradiation. The latent buildup is thermally activated. with an activation energy of approximately 0.47 ev. Within experimental uncertainty, this is equal to the activation energy ( approximately 0.45 eV) for the diffusion of molecular hydrogen in bulk fused silica. Latent interface-trap buildup can degrade the performance of devices in low-dose-rate radiation environments (e.g. space). >