Memory Latency Research Articles

A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems

Future CPU-manycore heterogeneous systems can provide high peak throughput by integrating thousands of simple, independent, energy-efficient cores in a single die. However, there are two key challenges to translating this high peak throughput into improved end-to-end workload performance: (1) manycore co-processors rely on simple hardware putting significant demands on the software programmer; and (2) manycore co-processors use in-order cores that struggle to tolerate long memory latencies. To address the manycore programmability challenge, this paper presents a dense and sparse tensor processing framework based on PyTorch that enables domain experts to easily accelerate off-the-shelf workloads on CPUmanycore heterogeneous systems. To address the manycore memory latency challenge, we use our extended PyTorch framework to explore the potential for decoupled access/execute (DAE) software and hardware mechanisms. More specifically, we propose two software-only techniques, naive-software DAE and systolic-software DAE, along with a lightweight hardware access accelerator to further improve area-normalized throughput. We evaluate our techniques using a combination of PyTorch operator microbenchmarking and real-world PyTorch workloads running on a detailed register-transfer-level model of a 128-core manycore architecture. Our evaluation on three real-world dense and sparse tensor workloads suggest these workloads can achieve approximately 2-6× performance improvement when scaled to a future 2,000-core CPU-manycore heterogeneous system compared to an 18-core out-of-order CPU baseline, while potentially achieving higher area-normalized throughput and improved energyefficiency compared to general-purpose graphics processing units.

ADC-PIM: Accelerating Convolution on the GPU via In-Memory Approximate Data Comparison

Recently, convolutional neural networks (CNN) have been widely used in image processing and computer vision. GPUs are often used to accelerate the CNN, but performance is limited by high computational costs and memory usage of the convolution. Prior studies exploited approximate computing to reduce the computational costs. However, they only reduced the amount of the computation, thereby its performance is bottlenecked by the memory bandwidth due to an increased memory intensity. In addition, load imbalance between warps caused by approximation also inhibits the performance improvement. In this paper, we propose a processing-in-memory (PIM) solution that reduces the amount of data movement and computation through the <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</u> pproximate <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</u> ata <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</u> omparison (ADC-PIM). Instead of determining the value similarity after loading the data to the GPU, the ADC-PIM unit located on 3D-stacked memory compares the similarity and transfers only the selected representative data to the GPU. The GPU performs convolution on the representative data transferred from the ADC-PIM, and reuses the calculated results based on the similarity information. To reduce the increase in memory latency caused by the in-memory data comparison, we propose a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">two-level</i> PIM architecture that exploits both the DRAM bank and TSV stage. By dividing the comparisons into multiple banks and then merging the results on the TSV stage, the ADC-PIM effectively hides the delay caused by the comparisons. To ease the load balancing on the GPU, the ADC-PIM performs <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">data reorganization</i> by assigning the representative data to addresses that are computed based on the comparison result. Experimental results show that the proposed ADC-PIM provides a 43% speedup and 32% energy saving with less than a 1% accuracy drop.

An ASIP for Neural Network Inference on Embedded Devices with 99% PE Utilization and 100% Memory Hidden under Low Silicon Cost.

The computation efficiency and flexibility of the accelerator hinder deep neural network (DNN) implementation in embedded applications. Although there are many publications on deep neural network (DNN) processors, there is still much room for deep optimization to further improve results. Multiple dimensions must be simultaneously considered when designing a DNN processor to reach the performance limit of the architecture, including architecture decision, flexibility, energy efficiency, and silicon cost minimization. Flexibility is defined as the ability to support as many multiple networks as possible and to easily adjust the scale. For energy efficiency, there are huge opportunities for power efficiency optimization, which involves access minimization and memory latency minimization based on on-chip memory minimization. Therefore, this work focused on low-power and low-latency data access with minimized silicon cost. This research was implemented based on an ASIP (application specific instruction set processor) in which an ISA was based on the caffe2 inference operator and the hardware design was based on a single instruction multiple data (SIMD) architecture. The scalability and system performance of our SoC extension scheme were demonstrated. The VLIW was used to execute multiple instructions in parallel. All costs for data access time were thus eliminated for the convolution layer. Finally, the processor was synthesized based on TSMC 65 nm technology with a 200 MHz clock, and the Soc extension scheme was analyzed in an experimental model. Our design was tested on several typical neural networks, achieving 196 GOPS at 200 MHz and 241 GOPS/W on the VGG16Net and AlexNet.

Plant derived Nano-11 particle adsorbed with stimulator of interferon genes adjuvant and split influenza virus antigens elicits the cross-protective immunity in pigs

Abstract We evaluated the performance of split swine influenza A virus (SwIAV) H1N2 antigens with a plant-derived nanoparticle adjuvant (Nano-11) or its combination with a synthetic STING agonist ADU-S100 (NanoS100). Specific pathogen free pigs were vaccinated twice via intramuscular (IM) and intradermal (ID) routes and challenged with a virulent heterologous H1N1. Animals vaccinated IM or ID with H1N2-ADU-S100-Nano-11 had significantly increased cross-reactive IgG and IgA titers in serum, nasal secretion and bronchoalveolar lavage fluid. There was a significant increase of IFNγ+ effector memory T-helper/memory cells and late effector cytotoxic T cells (CTLs), IL-17A+ central and effector memory T-helper/memory cells, IL-17A+ early effector CTLs, and CXCL10+ plasmacytoid dendritic cells in the PBMCs of the ID injected H1N2-ADU-S100-Nano-11 compared to H1N2-Nano-11 group. The frequency of IFNγ+ late effector CTLs and effector memory T-helper/memory cells and IL-17A+ late effectorCTLs, as well as in lungs CXCL10+ plasmacytoid dendritic cells was increased in PBMCs of IM injected H1N2-ADUS100-Nano-11 pigs. Increased expression of IL-4 and IL-6 mRNA was observed in tracheobronchial lymph nodes of IM Nano-11 based vaccinates following challenge. Furthermore, the challenge virus load in the lungs and nasal passage was undetectable in IM H1N2+ADU-S100-Nano-11 vaccinates by day 6 post infection along with reduced macroscopic lung lesions. In conclusion, despite vast genetic difference (77% HA gene identity) between the H1N2 and H1N1 SwIAV, the NanoS100 adjuvanted vaccine elicited cross protective immune responses, suggesting the potential role of this combination adjuvant in inducing cross-protective immunity in pigs. Supported by USDA National Institute of Food and Agriculture, AFRI project 2019-67015-29814

Memory-related Induction Mechanisms Trigger Persistent Hyperexcitability of Nociceptors

Persistent hyperexcitability of primary nociceptors is a major contributor to diverse forms of chronic pain. While much is known about mechanisms that maintain persistent hyperexcitability, little is known about induction mechanisms. Interesting parallels have been noted between processes that can induce long-lasting nociceptor hyperexcitability and mechanisms involved in memory formation (e.g., Weragoda et al., 2004; J Neurosci 24:10393; Price et al., 2015, Prog Mol Biol Transl Sci, 131:409). We have developed an in vitro model to test the hypothesis that cellular processes important for the induction of late long-term synaptic potentiation (L-LTP) and memory in the hippocampus can also induce long-term hyperexcitability (LTH) of dissociated rat nociceptor somata. We have begun by testing whether nociceptor LTH can be induced by cAMP signaling involving PKA activity, CREB activity, gene transcription, and protein synthesis. Rat DRG neurons were dissociated and cultured overnight. Beginning 1 h after dissociation, neurons were incubated for 6 h with the adenylyl cyclase activator, forskolin, or a Gs-coupled serotonin receptor (5-HT4R) agonist, prucalopride. Other neurons received co-treatment with either a PKA inhibitor, H89; a CREB inhibitor, 666-15; a transcription inhibitor, actinomycin D; or a translation inhibitor, cycloheximide, at concentrations known to block the induction of hippocampal L-LTP. Whole-cell patch recordings under current-clamp were made 12-24 h after washout. The early treatment with forskolin or prucalopride induced LTH manifested as depolarization of resting membrane potential and increased action potential generation when neurons were further depolarized artificially to -45 mV for 30 s. Co-treatment during induction by prucalopride with H89, 666-15, actinomycin D, or cycloheximide significantly reduced LTH. These results support the hypothesis that conserved, memory-related mechanisms can induce nociceptor alterations known to promote persistent pain. This preparation enables efficient, detailed examination of numerous potential induction mechanisms, and might reveal new pharmacological targets for preventing the transition to chronic pain. Grant support from NIH grants NS091759 and NS111521.

Algorithm/architecture solutions to improve beyond uniform quantization in embedded DNN accelerators

The choice of data type has a major impact on speed, accuracy, and power consumption of deep learning accelerators. Quantizing the weights and activations of neural networks to integer based computation is an industry standard for reducing memory footprint and computation cost of inference in embedded systems. Uniform weight quantization can be used for tasks where accuracy drop can be tolerated. However, the drop in accuracy due to a uniform quantization might be non-negligible especially when performed on shallow networks, complex computer vision tasks, or with lower-bit integers.In this paper, we introduce a software and a hardware solution to improve on a baseline integer based uniform quantization so that it can be run on lower power systems and with even less bits. We also introduce a novel encoding technique on top of our software solution specific for partial sums to significantly reduce memory footprint, latency and energy consumption due to movement of partial sums. The proposed SW solution exploits non-uniform piece-wise linear quantization to improve accuracy by capturing bell shaped distribution of weights while still using INT-based computation units. The proposed partial sum encoding can be applied to the partial sums regardless of uniform or non-uniform quantization. The proposed HW solution can either combine integers to make larger integers or turn them into Floating-Point operations so that various levels can have various precisions or data types, if necessary. To do so, we studied upper limits of precision we need in our compute units to support floating point inner product operations. It turns out that we can improve upon integer IPUs to perform accurate floating-point operations without introducing large shift units or wide adder trees.Our proposed SW solution (PWLQ) achieves the state-of-the-art results on all cases and it outperforms all other methods with a large margin. The proposed partial sum encoding technique effectively compresses the partial sum of networks like Resnet-50 down to 12bits (from Int64/32) without loss in accuracy. The proposed HW architecture achieves area improvements of up to 46% in TOPS/mm2 with power efficiency improvements of up to 63% in TOPS/W when compared to state of the art mixed precision implementation.

Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores

Exploiting memory-level parallelism (MLP) is crucial to hide long memory and last-level cache access latencies. While out-of-order (OoO) cores, and techniques building on them, are effective at exploiting MLP, they deliver poor energy efficiency due to their complex and energy-hungry hardware. This work revisits slice-out-of-order (sOoO) cores as an energy-efficient alternative for MLP exploitation. sOoO cores achieve energy efficiency by constructing and executing slices of MLP-generating instructions out-of-order only with respect to the rest of instructions; the slices and the remaining instructions, by themselves, execute in-order. However, we observe that existing sOoO cores miss significant MLP opportunities due to their dependence-oblivious in-order slice execution, which causes dependent slices to frequently block MLP generation. To boost MLP generation, we introduce Freeway, a sOoO core based on a new dependence-aware slice execution policy that tracks dependent slices and keeps them from blocking subsequent independent slices and MLP extraction. The proposed core incurs minimal area and power overheads, yet approaches the MLP benefits of fully OoO cores. Our evaluation shows that Freeway delivers 12% better performance than the state-of-the-art sOoO core and is within 7% of the MLP limits of full OoO execution.

An efficient GPU acceleration technique for CBCT based on memory aware optimization scheme

Among many of the image reconstruction techniques; the Feldkamp-Davis-Kress (FDK) is considered the most practical algorithm that used in clinical cone-beam Computed Tomography (CT) technology. In this paper, we present a full memory-aware management optimization scheme to reconstruct high-resolution volumes for a large number of X-Ray images as projections based on an efficient GPU acceleration technique. The proposed optimization technique is a scheme for FDK acceleration, that sheds new light on 4 new strategies: (1) Overcome limited device memory by evaluating different four configurations to migrate input and output data in the CPU/GPU system, (2) Reduce data transfer time during the FDK execution by using a Unified Memory (UM) model with data prefetching feature during reconstruction for data migration between host and device, (3) Accelerate the bottleneck algorithm back-projection as a result of computation mitigation, and (4) Optimize projection data layout that led to better device memory access and overcomes memory latency problem before processing and computing on GPU. The experimental results based on the proposed method show that it took 21.17 sec and 101.76 sec to reconstruct high-resolution 1024 3 , 2048 3 - voxel volume from 1800 projection of 1024 2 and 2048 2 -pixel respectively. The performance resulted from our optimization technique considered on-the-fly reconstruction (real-time), which means it can process 85 projections per second for high-resolution volumes from a large number of projections to achieve accuracy and resolution for reconstructed volume. In the term of speedup, the proposed method can achieve 1.72 speedup to reconstruct the low-resolution volume 512 3 , 1.82 speedup for 1024 3 volume and 1.70 s p e e d u p f o r 2048 3 for highest resolution volumes over baseline implementation and optimized over previous reconstruction methods based on FDK.

Immunological features that associate with the strength of antibody responses to BNT162b2 mRNA vaccine against SARS-CoV-2

Predictive clinical factors associated with favorable responses to BNT162b2 mRNA vaccine against SARS-CoV-2 have been reported in some studies; however, there is a subgroup with low antibodytiters without well-known clinical factors reducing antibody responses. To clarify the immunological backgrounds that underlie the difference in antibody responses, we analyzed peripheral blood mononuclear cells (PBMCs) of each 20 individuals with a high anti-SARS-CoV-2 antibody titer and a low antibody titer out of 1774 healthcare workers who received BNT162b2 mRNA vaccine. A higher percentage of B cells before vaccination was associated with a higher antibody titer. Among B cells, naïve and transitional B cell frequencies were positively correlated with a higher antibody titer, whereas the frequencies of late memory B cells and plasmablasts were associated with a lower antibody titer. Fold change in the frequency of activated CD8+ T cells upon vaccination was also correlated with high antibody titers.

Efficient Hint-Based Event (EHE) Issue Scheduling for Hardware Multithreaded RISC-V Pipeline

Hardware multithreading is a common approach for tolerating memory latency by utilizing idle cycles and avoiding CPU stalling. Nowadays, multithreading architectures are commonly used across many processors and various embedded edge devices to improve performance. This work suggests a new multithreading in-order pipeline microarchitecture design for RISC-V and proposes an efficient event-based issue scheduling algorithm. The proposed scheduling algorithm is based on the unique RISC-V ISA that enables decoding of the instruction type in an early stage of the pipeline. The RISC-V-based multithreading architecture is evaluated using a dedicated software simulator. Simulation results show that the proposed algorithm outperforms the classical Round Robin and the coarse grain algorithms. The proposed architecture is evaluated using the standard MiBench benchmark and other common applications, demonstrating pipeline utilization improvement of up to about 26% in terms of IPC using four threads.

Inhibitory Metaplasticity in Juvenile Stressed Rats Restores Associative Memory in Adulthood by Regulating Epigenetic Complex G9a/GLP.

BackgroundExposure to juvenile stress was found to have long-term effects on the plasticity and quality of associative memory in adulthood, but the underlying mechanisms are still poorly understood.MethodsThree- to four week-old male Wistar rats were subjected to a 3-day juvenile stress paradigm. Their electrophysiological correlates of memory using the adult hippocampal slice were inspected to detect alterations in long-term potentiation and synaptic tagging and capture model of associativity. These cellular alterations were tied in with the behavioral outcome by subjecting the rats to a step-down inhibitory avoidance paradigm to measure strength in their memory. Given the role of epigenetic response in altering plasticity as a repercussion of juvenile stress, we aimed to chart out the possible epigenetic marker and its regulation in the long-term memory mechanisms using quantitative reverse transcription polymerase chain reaction.ResultsWe demonstrate that even long after the elimination of actual stressors, an inhibitory metaplastic state is evident, which promotes synaptic competition over synaptic cooperation and decline in latency of associative memory in the behavioral paradigm despite the exposure to novelty. Mechanistically, juvenile stress led to a heightened expression of the epigenetic marker G9a/GLP complex, which is thus far ascribed to transcriptional silencing and goal-directed behavior.ConclusionsThe blockade of the G9a/GLP complex was found to alleviate deficits in long-term plasticity and associative memory during the adulthood of animals exposed to juvenile stress. Our data provide insights on the long-term effects of juvenile stress that involve epigenetic mechanisms, which directly impact long-term plasticity, synaptic tagging and capture, and associative memory.

Hypermnesia and Amnesia: Remembering (with) the Body and Post-Conflict Memorials and Architectures

The article consists of two parts. The first part (§§ 1–2) investigates the indiscriminate and absolute remembering and forgetting of everything, hypermnesia and amnesia as the extreme terms that research has used and uses for the different phenomena of memory, both in individuals and in social and political forms. In the face of these shifts it is thus indispensable to re-establish a critique of the paradoxical effects of memory aids and, at the same time, to seek new forms of remembrance that by mixing an experiential dimension and public sphere refocus the attention on the connection between latency, tension and experiential triggers of involuntary memory and on the ability to break through the fictions of collective memory. On this basis, the second part of the article (§§ 3–4) analyses how the experience of political and racial deportation during World War II drastically changed the idea of memorial architecture. More specifically, the analysis deals with a kind of memorial device that must represent and memorialise persons whose bodies have been deliberately cancelled. The aim is to present and analyse the artistic and architectonic efforts to refer to those forgotten bodies, on the one hand, and on the other hand to point out how for these new kind of memorials the body of the visitor is asked to participate, both physically and emotionally, in this somehow paradoxical search for lost bodies, offering oneself as a substitute.

Spatial Data Dependence Graph Based Pre-RTL Simulator for Convolutional Neural Network Dataflows

In this paper, a new pre-RTL simulator is proposed to predict the power, performance, and area of convolutional neural network (CNN) dataflows prior to register-transfer-level (RTL) design. In the simulator, a novel approach is adopted to implement a spatial data dependence graph (SDDG), which enables us to model a specific dataflow alongside inter-instruction dependencies by tracking the status of each processing element (PE). In addition, the proposed pre-RTL simulator makes it possible to evaluate the impact of memory constraints such as latency and bandwidth. The latency-insensitive and bandwidth-insensitive PE controllers assumed in the proposed pre-RTL simulator guarantee both functional correctness and maximum performance, regardless of memory constraints. In particular, it is shown that the optimal distribution method of local memory bandwidth can reduce the accelerator execution time by up to 37.6% compared with the equal distribution method. For weight stationary (WS) and row stationary (RS) dataflows, the accelerator performance closely depends on memory constraints. The simulation results also show that the relative performances of dataflows depend on the layer shape of the convolutional layer. For example, for an identical hardware area in a standard convolutional layer of AlexNet, WS dataflows do not provide any performance gain over RS dataflows when the memory latency is sufficiently high. In addition, WS dataflows cannot fully reuse the input activation, thereby increasing local memory accesses, since the number of weights loaded at a specific time is limited. Moreover, in a depth-wise convolutional layer of MobileNet, WS dataflows tend to outperform RS dataflows even in the presence of large memory latency. The source code is available on the GitHub repository: <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/SDL-KU/SDDGSim</uri> .

EGCN: An Efficient GCN Accelerator for Minimizing Off-Chip Memory Access

As Graph Convolutional Networks (GCNs) have emerged as a promising solution for graph representation learning, designing specialized GCN accelerators has become an important challenge. An analysis of GCN workloads shows that the main bottleneck of GCN processing is not computation but the memory latency of intensive off-chip data transfer. Therefore, minimizing off-chip data transfer is the primary challenge for designing an efficient GCN accelerator. To address this challenge, optimization is initialized by considering GCNs as tiled matrix multiplication. In this paper, we optimize off-chip memory access from both the in- and out-of-tile perspectives. From the out-of-tile perspective, we find optimal tile configurations of given datasets and on-chip buffer capacity, then observe the dataflow across phases and layers. Inter-layer phase fusion dataflow with optimal tile configuration reduces data transfer of intermediate outputs. From the in-tile perspective, due to the sparsity of tiles, tiles have redundant data which does not participate in computation. Redundant data load is eliminated with hardware support. Finally, we introduce an efficient GCN inference accelerator, EGCN, specialized for minimizing off-chip memory access. EGCN achieves 41.9% off-chip DRAM access reduction, 1.49× speedup, and 1.95× energy efficiency improvement on average over the state-of-the-art accelerators.

Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs

Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memories (block RAMs and registers). HLS tools allow exploiting the memory hierarchy in a scratchpad-like fashion, requring a significant manual effort. We propose an automation of the FPGA memory management in Xilinx <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vitis HLS</i> through a fully-configurable C++ source-level cache. Each DRAM-mapped array can be associated with a private level 2 (L2) cache with one or more ports, and each port can optionally provide a level 1 cache. The L2 cache runs in a separate dataflow task with respect to the application accessing it. This solution isolates off-chip memory accesses and data buffering into dedicated dataflow tasks, resembling the load, compute, store design paradigm, but without the drawback of manual algorithm refactoring. Experimental results collected from an FPGA board show that our cache speeds up the execution of a variety of benchmarks by up to 60 times compared to the out-of-the-box solution provided by HLS, requiring very limited optimization effort. Our caches are not meant to compete with manually optimized implementations quality of results (QoR), but rather to significantly save design effort, in exchange for some QoR, to make the HLS flow a bit more software-like, allowing the designer to focus on algorithmic optimizations, rather than on explicit memory management. Moreover, caching could be the only feasible memory optimization for algorithms with data-dependent or irregular memory access patterns, but with good data locality.

Reducing GPU Energy Consumption by Packing Narrow-Width Operands

In this paper, we study the use of an Operand-Width-Aware Register (OWAR) packing mechanism for graphics processing unit (GPU) energy saving. In order to efficiently use the GPU register file (RF), OWAR employs a power gating method to shut down unused register sub-arrays in order to reduce dynamic and leakage energy consumption of RF. As the number of register accesses was reduced due to the packing of the narrow width operands, the dynamic energy dissipation was further decreased. Finally, with the help of RF usage optimized by register packing, OWAR allowed GPUs to support more thread-level parallelism (TLP) through assigning additional thread blocks on streaming multiprocessors (SMs) for general-purpose GPU (GPGPU) applications that suffered from the deficiency of register resources. The extra TLP opens opportunities for hiding more memory latencies and thus reducing the overall execution time, which can lower the overall energy consumption. We evaluated OWAR using a set of representative GPU benchmarks. The experimental results showed that compared to the baseline without optimization, OWAR can reduce the GPGPU’s total energy up to 29.6% and 9.5% on average. In addition, OWAR achieved performance improvement up to 1.97X and 1.18X on average.

An Efficient and Low-Latency Deep Inertial Odometer for Smartphone Positioning

The Global Positioning System (GPS) is not an effective solution for pedestrian indoor navigation using embedded devices because of poor signal penetration and high power requirements. Indoor positioning based purely on commercial-grade inertial measurement units (IMUs) may provide a good alternative but their significant noise and random bias must be eliminated. Although Kalman filters and pedestrian dead reckoning helped reduce the errors using IMUs, these methods cannot prevent the divergence of estimated position error. Deep learning was proposed for accurate position estimation with IMUs. Despite the progress, robust position estimation in mobile embedded devices using deep learning has not been established yet because of memory requirements, latency and inaccurate position estimation especially for stationary pedestrians. In this study, we present an efficient embedded deep learning approach for robust, real-time and accurate pedestrian position estimation using commercial Android smartphone IMUs. We first extended a publicly available deep inertial navigation dataset (OxIOD) with stationary data to enhance the positioning accuracy for both steady state and motion. Next, we trained and tested a deep learning architecture that yields a higher positioning accuracy with 50% lower network latency and 31% lower network size compared with earlier deep positioning networks such as IONet. Our real-time tests of the model in an Android smartphone indicated that the extension for the dataset reduces the position shift when the smartphone is stationary. Since our embedded deep learning solution simultaneously decreases the positioning error, latency and memory requirements, the solution paves the way for numerous practical indoor navigation applications.

Identifying Changes in Peripheral Lymphocyte Subpopulations in Adult Onset Type 1 Diabetes.

T- and B-lymphocytes play an important role in the pathogenesis of type 1 diabetes (T1D), a chronic disease caused by the autoimmune destruction of the insulin-producing cells in the pancreatic islets. Flow cytometry allows their characterization in peripheral blood, letting to investigate changes in cellular subpopulations that can provide insights in T1D pathophysiology. With this purpose, CD4+ and CD8+ T cells (including naïve, central memory, effector memory and terminally differentiated effector (TEMRA), Th17 and Tregs) and B cells subsets (naïve, unswitched memory, switched memory and transitional B cells) were analysed in peripheral blood of adult T1D patients at disease onset and after ≥2 years using multiparametric flow cytometry. Here we report changes in the percentage of early and late effector memory CD4+ and CD8+ T cells as well as of naïve subsets, regulatory T cells and transitional B cells in peripheral blood of adult patients at onset of T1D when compared with HD. After 2 years follow-up these changes were maintained. Also, we found a decrease in percentage of Th17 and numbers of T cells with baseline. In order to identify potential biomarkers of disease, ROC curves were performed being late EM CD4 T cell subset the most promising candidate. In conclusion, the observed changes in the percentage and/or absolute number of lymphocyte subpopulations of adult T1D patients support the hypothesis that effector cells migrate to the pancreas and this autoimmune process perseveres along the disease. Moreover, multiparametric flow allows to identify those subsets with potential to be considered biomarkers of disease.

Comparing behavior following binge ethanol in adolescent and adult DBA/2 J mice

The adolescent brain undergoes maturation in areas critically involved in reward, addiction, and memory. Adolescents consume alcohol more than any other drug, typically in a binge-like manner. While adults also binge on alcohol, the adolescent brain is more susceptible to ethanol-related damages due to its ongoing development, which may result in persistent behavioral and physical changes, including differences in myelination in the frontal cortex. Sex also impacts ethanol metabolism and addiction progression, suggesting females are more sensitive than males. This study addressed memory, sociability, ethanol sensitivity, and myelin gene expression changes due to binge ethanol, sex, and age. DBA/2 J males and females were exposed to intermittent binge ethanol (4 g/kg, i.g.) from postnatal day (PND) 29–42 or as adults from PND 64–77. Age groups were tested for behaviors at the early phase (24 h – 7 days) and late phase (starting 3 weeks) after the last dose. Adult prefrontal cortex was collected at both phases. Adolescent ethanol impaired late phase memory while adult ethanol showed no impairment. Meanwhile, adolescent males showed early phase tolerance to ethanol-induced locomotor activation, while adult females showed tolerance at both phases. Adult-treated mice displayed reductions in social interaction. Adult ethanol decreased Mal expression, a gene involved in myelin integrity, at the early phase. No differences in myelin gene expression were observed at the late phase. Thus, adolescent binge ethanol more severely impacts memory and myelin gene expression compared to adult exposure, while adult mice display ethanol-induced reductions in social interaction and tolerance to ethanol’s locomotor activation.

Sleep and hippocampal function during an associative memory task are influenced by surgical menopause at midlife

AbstractBackground17β‐estradiol loss is related to Alzheimer’s disease (AD) risk factors, including disordered sleep and associative memory decrements (Gervais et al., 2017; Rentz et al., 2017). Women have higher risk for AD than men, and those with mid‐life 17β‐estradiol loss due to surgical menopause, including bilateral salpingo‐oophorectomy (BSO) before age 48, have even higher risk (Rocca et al., 2007). Our learning objective was to investigate whether sleep and associative memory in women with BSO (mean age 44‐46) would be comparable to those with spontaneous/natural menopause (SM; mean age 57), and whether 17β‐estradiol‐based hormone therapy (ET) might mitigate these effects.MethodWe assessed sleep using the average of three nights of portable polysomnography (Temec) in women with BSO either taking ET (BSO+ET; n=16), or not (BSO; n=18), and in older spontaneously menopausal women (SM; n=14). Using EEG (Fp1‐Fp2), we obtained sleep staging automatically (Neurobit Technologies). Participants also completed a face‐name associative memory task during functional magnetic resonance imaging. Recognition accuracy and brain activation during encoding were measured.ResultBSO exhibited reduced sleep efficiency compared to BSO+ET. For BSO, there was no relationship between percent of total sleep time in N3 and hippocampal activation during associative encoding, even though percent of total sleep time in N3 was negatively associated with hippocampal activation during associative encoding in BSO+ET. For all groups, including BSO, lower latency to consolidated N3 correlated with better associative memory accuracy. There were no group differences in associative memory accuracy. In contrast to BSO, SM showed significantly longer latency to consolidated N3 than BSO+ET.ConclusionYounger women with BSO have comparable sleep to older women in SM. In younger women with BSO, ET improves sleep efficiency. Further, while associative memory may be disrupted by increased latency to consolidated N3 in all women, BSO and BSO+ET showed similar associative memory accuracy and latency to consolidated N3. Only BSO+ET exhibited a significant correlation between hippocampal activity during associative encoding and time spent in N3, indicating that ET may support the negative relationship between N3 and hippocampal function. Overall, ET in younger women with BSO potentially ameliorates poor sleep and associative memory decrements.