Large Vth Research Articles

Effects of excess oxygen on operation characteristics of amorphous In-Ga-Zn-O thin-film transistors

Operation characteristics of amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) were improved to a subthreshold voltage swing (S) of 217 mV (decade)−1, a mobility of ∼11.4 cm2 (Vs)−1, and a threshold voltage (Vth) of 0.1 V by O3 annealing at a temperature as low as 150 °C. However, the O3 annealing at 300 °C caused serious deterioration and exhibited a bistable transition between a large S state and a large Vth state. This transition is attributed to incorporation of excess oxygen and associated subgap defects with a negative-U characteristic. It also explains why a-IGZO channels deposited at high oxygen pressures do not produce operating TFTs.

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology

The Effect of Oxygen Plasma on Activation Efficiency of Implanted Silicon in Gallium Arsenide

The effect of oxygen (O2) plasma on the threshold voltage (Vth) shift in gallium arsenide (GaAs) metal semiconductor field effect transistors (MESFETs), which were fabricated using ion implantation, was investigated. An O2 plasma process in barrel type reactor was found to cause a large Vth difference in MESFETs between wafers that were processed in the same batch. Numerical calculations were performed to understand the phenomena quantitatively. Experimental analyses, using secondary ion mass spectrometry (SIMS), transmission electron microscopy (TEM), Rutherford backscattering spectrometry (RBS) and capacitance–voltage (C–V) measurement, were employed to confirm the key factor in the Vth shift mechanism. As a result, it was demonstrated that the shift was caused not by the etching of the FET channel but by the degradation of the activation efficiency. The degradation was related to the excessive oxidation, which proceeded by pulling up the substrate atoms and increased vacancy type defects in the channel.

High-Performance Accumulated Back-Interface Dynamic Threshold SOI MOSFET (AB-DTMOS) with Large Body Effect at Low Supply Voltage

A high-performance accumulated back-interface dynamic threshold silicon-on-insulator metal-oxide-semiconductor field effect transistor (AB-DTMOS) with a large body effect at low supply voltage (Vdd< 0.5 V) is proposed for low-power applications. In AB-DTMOS, the back interface between the non-doped thin SOI and the buried oxide is accumulated by a large negative substrate bias, and the gate electrode is connected to this electrically induced body. AB-DTMOS realizes an ideal low/ultrahigh step channel profile electrically and achieves the maximum body effect. At fixed Vth, the body effect factor (γ) of AB-DTMOS is twice as large as that of the conventional uniformly doped channel DTMOS, because the channel depletion layer width of AB-DTMOS is half that of the conventional DTMOS. Experimental results show a steep subthreshold slope, a high current drive due to a large Vth shift, and a suppressed short channel effect.

Low Dislocation-Density and Vacancy-Rich Glassy-Pinning Quasi GaAs Crystal by Liquid-Encapsulated Czochralski Growth

ABSTRACTNot all threshold voltage (Vth) scattering of Si-implanted metal-semiconductor field- effect- transistors (MESFETs) on low dislocation density and semi-insulating (S.I.) liquid- glass encapsulation Czochralski (LEC) GaAs crystals grown at relatively high pull-speed were small. By comparison with the Lang x-ray topographs of the wafers, it was found that x-ray topograph contrast variations reflected on the films did not correspond with Vth variations of the wafers at all. Especially, in low dislocation density regions, which are in white regions on the films of the x-ray topographs, very large Vth turbulences were observed. We believe that dislocation-less in LEC GaAs crystals causes large Vth turbulences of Si-implanted MESFETs and that frozen cell-lattice-structure large turbulences by pinning centers associated with vacancies like glass cause large Vth turbulences.

Implanted Si atoms shifting between Ga sites and As sites by thermal stress in conductive-layer GaAs crystals on semi-insulating substrates

Large (0.8 V order) discrepancies of threshold voltage Vth between the predicted Vth values by the Lindhard–Scharff–Schio/tt Gaussian approximate calculation and the Vth of the tungsten nitride (WNx) self-alignment (SA) gate GaAs metal-semiconductor field-effect transistors (MESFETs) were observed. These discrepancies were confirmed by the comparison of the Vth of the WNx-SA-gate MESFETs and the Vth of the (N+: high carrier concentration layers self-aligned of source-drain electrodes)-less conventional MESFETs on 2-in.-diam semi-insulating substrates from liquid-encapsulated-Czochralski-technique-grown 〈100〉 boules. The discrepancy was also analyzed by the capacitance-voltage (C-V) measurement of large-diameter (440 μm) Schottky diodes which were built into the MESFET arrays. It was found that for obtained SA-process carrier depth profiles (Si, 150 keV, 3×1012 cm−2) the carrier concentration at a depth of 0.25 μm decreased from 5.3×1016 to 2.0×1016 cm−3, but, on the other hand, the peak carrier concentration slightly decreased from 12.8×1016 to 12.4×1016 cm−3. By the calculation for Vth on the basis of the actual C-V carrier depth profiles, it was found that the carrier concentration decrease was comparable to the Vth variation (0.8 V). Furthermore, the Vth variation of the shallow channel implantation (50 keV) was comparable to that of the deep channel implantation (150 keV). As a result of the experiment and analysis, it was found that the large Vth variation for the SA N+ process was caused by reoccupation (Ga sites to As sites) of implanted Si atoms in the channel active-layer crystal by tensile stress formed by the thermal-expansion coefficient difference between chemical-vapor deposition (CVD) phosphosilicate glass (or CVD SiO2) film and (100) GaAs substrate crystal. The Si atom reoccupation quantity was, for the first time, explained by the Si atom compensation ratio equation as a function of the bond length (Si-As and Si-Ga) variation, an equation which was again derived based on Otsuki’s work on the Si atom Gibbs free energy in GaAs crystal, using the data of thermal-expansion coefficients for SiO2, GaAs, and WNx in the report of Katz and Dautremont-Smith [J. Appl. Phys. 67, 6237 (1990)] and in the report of Lahav, Grim, and Blech [J. Appl. Phys. 67, 734 (1990)]. Moreover, the analysis suggests that local stress or local distortion, which is introduced by the implanted Si atom itself into the GaAs crystal, performs an important role for the Si atom electrical activation efficiency.