Large SoCs Research Articles

Communication modeling of multicast in all-port wormhole-routed NoCs

Multicast is one of the most frequently used collective communication operations in multi-core SoC platforms. Bus as the traditional interconnect architecture for SoC development has been highly efficient in delivering multicast messages. Since the bus is non-scalable, it can not address the bandwidth requirements of the large SoCs. The networks on-chip (NoCs) emerged as a scalable alternative to address the increasing communication demands of such systems. However, due to its hop-to-hop communication, the NoCs may not be able to deliver multicast operations as efficiently as buses do. Adopting multi-port routers has been an approach to improve the performance of the multicast operations in interconnection networks. This paper presents a novel analytical model to compute communication latency of the multicast operation in wormhole-routed interconnection networks employing asynchronous multi-port routers scheme. The model is applied to the Quarc NoC and its validity is verified by comparing the model predictions against the results obtained from a discrete-event simulator developed using OMNET++.

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment.

Energy reduction through crosstalk avoidance coding in networks on chip

Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near future. With this ever increasing degree of integration, design of communication architectures for large, multi-core SoCs is a challenge. Traditional bus-based systems will no longer be able to meet the clock cycle requirements of these big SoCs. Instead, the communication requirements of these large multi processor SoCs (MP-SoCs) are convened by the emerging network-on-chip (NoC) paradigm. Crosstalk between adjacent wires is an important signal integrity issue in NoC communication fabrics and it can cause timing violations and extra energy dissipation. Crosstalk avoidance codes (CACs) can be used to improve the signal integrity by reducing the effective coupling capacitance, lowering the energy dissipation of wire segments. As NoCs are built on packet-switching, it is advantageous to modify data packets by including coded bits to protect against the negative effects of crosstalk. By incorporating crosstalk avoidance coding in NoC data streams and organizing the CAC-encoded data packets in an efficient manner, so that total number of encoding/decoding operations can be reduced over the communication channel, we are able to achieve lower communication energy, which in turn will help to decrease the overall energy dissipation.

A Survey and Taxonomy of GALS Design Styles

Single-clocked digital systems are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous, locally synchronous (GALS). To minimize time to market, large SoC designs must integrate many functional blocks with minimal design effort. These blocks are usually designed using standard synchronous methods and often have different clocking requirements. A GALS approach can facilitate fast block reuse by providing wrapper circuits to handle interblock communication across clock domain boundaries. SoCs may also achieve power savings by clocking different blocks at their minimum speeds. For example, Scott et al. describe the advantages of GALS design for an embedded-processor peripheral bus.

Fixed-outline floorplanning using robust evolutionary search

Typical floorplanning concerns a series of objectives, such as area, wirelength, and routability, etc., with various aspect ratios of modules in a free-outline regime. However, in a hierarchical design flow for very large ASICs and SoCs, a floorplan can be completely useless for a situation where its outline is dissatisfied. In this paper, we study the fixed-outline floorplanning problem that is more applicable to the hierarchical design style. We develop an efficient algorithm based on robust evolutionary search and achieve substantially improved success rate. We also propose a new approach to handle soft modules to further adjust the generated floorplan to fit into the prescribed chip outline. The effectiveness of our methods is demonstrated on several large cases of MCNC and GSRC benchmarks.

ChronoSym: a new approach for fast and accurate SoC cosimulation

The early validation of modern SoC is not anymore feasible using traditional cycle-accurate cosimulations. These are based on the concurrent execution between SW running on multiple Instruction Set Simulators and HW simulators. The challenge is then speeding-up the simulation, without sacrificing the accuracy of traditional methods. The key contribution of this paper is a novel fast and accurate HW/SW cosimulation approach, allowing to handle large SoCs, while reducing the design cycle. The key underlying concepts are timed native SW execution, combined with detailed HW/SW interaction models. This approach is implemented in ChronoSym tool and applied to two real SoC applications.

Fixed-outline floorplanning: enabling hierarchical design

Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported . A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fixed-outline modes. We use Parquet-1 to floorplan a design, with approximately 32000 cells, in 37 min using a top-down, hierarchical paradigm.

Using RTL-to-C++ translation for large SoC concurrent engineering: a case study

RTL-to-C translation can be used to help verify the design of complex SoCs by letting generated models run production code at high speed. The authors describe the technique used to replace hardware emulation during the development of a 5 million gate device for the DSL market.

Detecting signal-overshoots for reliability analysis in high-speed system-on-chips

The rising level of complexity and speed of SoC makes it increasingly vital to test adequately the system for signal integrity. Voltage overshoot is one of the integrity factors that has not been sufficiently addressed for the purpose of testing and reliability. Overshoots are known to inject hot-carriers into the gate oxide and cause permanent degradation of MOSFET transistors' performance. This performance degradation creates a serious reliability concern. Unfortunately, accurate parasitic extraction and simulation to detect the interconnect problems is very time consuming and very sensitive to the circuit characteristics and thus is not practical for large SoC. This paper presents a built-in chip methodology to detect and measure the signal overshoots occurring on the interconnects of high-speed system-on-chips. This built-in test strategy does not require external probing or signal waveform monitoring. Instead, the overshoot detector cells monitor signals received by a core (e.g. from the system bus) and record the occurrence of overshoots over a period of operation. The overshoot information accumulated by these cells can be compressed and scanned out efficiently And inexpensively for final quality grading, reliability analysis and diagnosis.