Large-scale Wafer Research Articles

Wafer-Scale Patterning Integration of Chiral 3D Perovskite Single Crystals toward High-Performance Full-Stokes Polarimeter.

Chiral three-dimensional (3D) perovskites exhibit exceptional optoelectronic characteristics and inherent chiroptical activity, which may overcome the limitations of low-dimensional chiral optoelectronic devices and achieve superior performance. The integrated chip of high-performance arbitrary polarized light detection is one of the aims of chiral optoelectronic devices and may be achieved by chiral 3D perovskites. Herein, we first fabricate the wafer-scale integrated full-Stokes polarimeter by the synergy of unprecedented chiral 3D perovskites (R/S-PyEA)Pb2Br6 and one-step capillary-bridge assembly technology. Compared with the chiral low-dimensional perovskites, chiral 3D perovskites present smaller exciton binding energies of 57.3 meV and excellent circular dichroism (CD) absorption properties, yielding excellent circularly polarized light (CPL) photodetectors with an ultrahigh responsivity of 86.7 A W-1, an unprecedented detectivity exceeding 4.84 × 1013 Jones, a high anisotropy factor of 0.42, and high-fidelity CPL imaging with 256 pixels. Moreover, the anisotropic crystal structure also enables chiral 3D perovskites to have a large linear-polarization response with a polarized ratio of 1.52. The combination of linear-polarization and circular-polarization discrimination capabilities guarantees the achievement of a full-Stokes polarimeter. Our study provides new research insights for the large-scale patterning wafer integration of high-performance chiroptical devices.

Unsupervised Representation Learning for Large-Scale Wafer Maps in Micro-Electronic Manufacturing

Recognition of wafer map defect patterns is essential for evaluating the reliability of micro-electronic manufacturing. Due to the difficulty of labeling, the available large-scale wafer maps are raw data without labeling. The scarcity of labeled samples reduces the defect pattern recognition accuracy of popular deep convolutional neural networks. To overcome this problem, we propose a wafer map deep clustering (WMDC) model. It learns generic representations from unlabeled datasets in an unsupervised manner. A prototype metric loss during training helps to learn the semantic features of the categories. We improve the recognition accuracy of the model when trained using scarce labeled data by transferring the weights of unsupervised pretraining. Experiments on WM811K and MixedWM38 wafer datasets demonstrate that the WMDC model is capable of obtaining robust prior representations from the unlabeled wafer maps. Accuracies of 97.43% and 98.74% are obtained when fine-tuning using scarce labeled data from both datasets, respectively.

Regulated and Gradual Polymorph Transition By Thermal and Plasma Treatment on Transition Metal Dichalcogenides

Transition metal dichalcogenides (TMDs) have two different phase structure which exhibit different properties. Generally, it can be classified into 1T (metallic) and 2H (semiconductor) phase structures according to the relative atomic direction of the TMDs. Currently, the utilization of two-dimensional (2D) materials is limited due to the lack of an appropriate phase control method of TMDs. There are several phase control methods reported so far (post-treatment chemical process, lattice deformation of physical crystals due to ion collision, phase control of materials through strain, etc.), but the disadvantages of requiring additional processes and low yield are limited for practical usage of those method. In this research, we conducted a study on gradual phase control of TMDs according to substrate temperature (150, 200, 250, 300, and 350°C) while other plasma parameters were kept constant (power, pressure, processing time, and gas ratio). By controlling the phase, the versatility of TMDs is dramatically improved. 1T-TMDs basal plane plays a crucial role as catalytically active site to enhance electrochemical properties more than 2H-TMDs. 1T-TMDs used as a hydrogen generation catalyst has been proposed as an alternative to noble metals (e.g., Pt, Ir, Ru). This is because 1T-TMDs have a metallic property and thus have dense catalytically active sites as edge and basal plane, which can be used as an electrochemical catalyst. However, the problem of (1T-TMDs) manufactured in the conventional way is that the unstable properties at room temperature of them. During the low-temperature plasma process, ion bombardment onto the substrate induces a grain boundary of several nano sizes to expand the active site per area of the surface crystal structure resulting in high catalytic activity. In addition, the possibility of large-scale production was presented on large-scale wafer synthesis, and the original phase of 1T-TMDs was preserved after the 1,000 HER cycle to prove robustness and durability. On the other hand, in the case of (2H-TMDs), instead of showing low catalytic activity, the existence of band gap makes them favorable for semiconductor device applications such as photodiode, transistor, and neuromorphic computing. In this study, by using the sputtered MoS2 and WS2 to control the ratio of different polymorph, memristive switching (RS) is investigated. Similarly, by ion bombardment onto substrates in a low-temperature plasma process, a few nano-sized particle boundaries were induced, creating a defect on the material surface. An experiment was conducted in which filaments are mimicking artificial neural networks and then ruptured under electrical bias. However, the reproducibility of filament formation for 2H-TMDs was relatively low, and the formed filament was relatively unstable. Therefore, it was intended to form a kind of 'road' to solve this problem. Here, the road was using a 1T-TMDs structure with high catalytic activity. The mixed phase of TMDs consist of a different phase (1T and 2H) structure, which depends on their process temperature. Diversity of process temperature results in various phase ratio into the material structure. Gradual phase change from 1T to 2H at various temperature (150, 200, 250, 300, and 350 °C) confirmed by X-ray photoelectron spectroscopy. By utilizing the mixed phase of TMDs, the metal filaments were formed along the 1T structure within 2H structure, which showing uniform RS behavior. Higher reproducibility was obtained for mixed phase structure than the 2H-TMDs and secured stability. In conclusion, by presenting a research direction on how to control the TMDs’ phases, this study can increase the utilization of the 2D material while adjusting different phases together, rather than single usage of the 2D material phases such as 1T- and 2H-TMDs.Acknowledgement: This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education 2022R1A6A3A13063381 and 2022R1A3B1078163). And this work was also supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No.2022R1A4A1031182).

The physical improvement of copper deposition uniformity with the simulation models

The large-scale square wafer electroplating process was analyzed using the finite element method (FEM) in COMSOL Multiphysics®. The distribution of deposition thickness on the wafer was assessed using the Non-Uniformity (NU%). Several modifications were made to the geometry of the electrolyte tank, including anode mask, cathode mask, and auxiliary cathodes (firewalls), to enhance the uniformity of deposition thickness. In terms of the kinetic aspect, the current distribution modules employ the Butler-Volmer equation to depict the current density and overpotential on the wafer. The Electrode Shell approach was utilized to account for the reduction in internal wafer resistance resulting from the growth of the copper seed layer. This enabled a more accurate simulation of the potential distribution on the wafer, bringing it closer to real-world conditions. Through the analysis of experimental data using three different models, it was observed that Model 2, which incorporated a coupled Electrode Shell with Secondary Current Distribution, provided the best simulation results for this experiment. The NU% value obtained from the experiment was 23.81%, which compared favorably to the simulated value of 23.46%. Consequently, the accuracy of the simulation reached an impressive 98.5%.

Implementation of Large Scale Deep Learning Non-Destructive Methods for Characterizing 4H-SiC Materials

A whole wafer method for industrial high volume, non-destructive characterizing of extended defects is demonstrated for 150 mm and 200 mm 4H-SiC wafers. Deep learning (DL) coupled with non-destructive techniques (NDT, DL-NDT) involving high volume, fast optical microscopy methods correlates industry accepted chemistry and physics-based etch and diffraction techniques for defect characterization. The application of the DL-NDT method is shown to reproduce defect distributions achieved by accepted etch techniques for extended defects of threading dislocations (TD), basal plane dislocations (BPD), and threading screw dislocations (TSD). An example of algorithm development is described to show progress toward implementing the method, as well as DL-NDT defect density compared to etch density for multiple wafers. The development status for implementing this technique for large-scale industrial wafer production includes etch validation of the results to ensure the technique is consistent and reliable. The ability to use this non-destructive technique ultimately will result in better correlation with device behavior and provide feedback to crystal growth processes to improve substrate wafers, while reducing the need for etch methods.

Sidewall Modification Process for Trench Silicon Power Devices

In this study, trench sidewall modification processes were designed to improve profile uniformity and thereby enhance the electrical performance of silicon power devices in large-scale production. The effects of trench sidewall modification on the morphology, structure and electrical properties were studied. Plasma-induced damage in etching processes was also observed and briefly explained. Straight and smooth sidewall profiles were achieved through adjusting the SF6/CHF3 proportion in a combined etchant gas flow in the main etching procedure. By comparing HRSEM images from different etching protocols, it was evident that an enhanced CHF3 flow formed a proper passivation of the sidewall, eliminating the ion damages that are common in current main etch steps. To address the impurities introduced from the etchant gas and improve the gate oxide uniformity, further steps of depolymerization were applied in a plasma asher chamber, followed by wet clean steps. In the meantime, the plasma-induced charge accumulation effect was reduced by UV curing. Improved trench sidewall profiles and the gate oxide uniformity contributed to a lower leakage current between the gate and source terminals, leading to an overall yield enhancement of device properties in large-scale silicon wafer fabrication.

ReS2 on GaN Photodetector Using H+ Ion-Cut Technology.

The wafer-scale single-crystal GaN film was transferred from a commercial bulk GaN wafer onto a Si (100) substrate by combining ion-cut and surface-activated bonding. Well-defined, uniformly thick, and large-scale wafer size ReS2 multilayers were grown on the GaN substrate. Finally, ReS2 photodetectors were fabricated on GaN and sapphire substrates, respectively, and their performances were compared. Due to the polarization effect of GaN, the ReS2/GaN photodetector showed better performance. The ReS2/GaN photodetector has a responsivity of 40.12 A/W, while ReS2/sapphire has a responsivity of 0.17 A/W. In addition, the ReS2/GaN photodetector properties have reached an excellent reasonable level, including a photoconductive gain of 447.30, noise-equivalent power of 1.80 × 10-14 W/Hz1/2, and detectivity of 1.21 × 1010 Jones. This study expands the way to enhance the performance of ReS2 photodetectors.

Detection and Prediction of Chipping in Wafer Grinding Based on Dicing Signal

Simple regression cannot wholly analyze large-scale wafer backside wall chipping because the wafer grinding process encounters many problems, such as collected data missing, data showing a non-linear distribution, and correlated hidden parameters lost. The objective of this study is to propose a novel approach to solving this problem. First, this study uses time series, random forest, importance analysis, and correlation analysis to analyze the signals of wafer grinding to screen out key grinding parameters. Then, we use PCA and Barnes-Hut t-SNE to reduce the dimensionality of the key grinding parameters and compare their corresponding heat maps to find out which dimensionality reduction method is more sensitive to the chipping phenomenon. Finally, this study imported the more sensitive dimensionality reduction data into the Data Driven-Bidirectional LSTM (DD-BLSTM) model for training and predicting the wafer chipping. It can adjust the key grinding parameters in time to reduce the occurrence of large-scale wafer chipping and can effectively improve the degree of deterioration of the grinding blade. As a result, the blades can initially grind three pieces of the wafers without replacement and successfully expand to more than eight pieces of the wafer. The accuracy of wafer chipping prediction using DD-BLSTM with Barnes-Hut t-SNE dimensionality reduction can achieve 93.14%.

Rapid, noncontact, sensitive, and semiquantitative characterization of buffered hydrogen-fluoride-treated silicon wafer surfaces by terahertz emission spectroscopy

Advances in modern semiconductor integrated circuits have always demanded faster and more sensitive analytical methods on a large-scale wafer. The surface of wafers is fundamentally essential to start building circuits, and quantitative measures of the surface potential, defects, contamination, passivation quality, and uniformity are subject to inspection. The present study provides a new approach to access those by means of terahertz (THz) emission spectroscopy. Upon femtosecond laser illumination, THz radiation, which is sensitive to the surface electric fields of the wafer, is generated. Here, we systematically research the THz emission properties of silicon surfaces under different surface conditions, such as the initial surface with a native oxide layer, a fluorine-terminated surface, and a hydrogen-terminated surface. Meanwhile, a strong doping concentration dependence of the THz emission amplitude from the silicon surface has been revealed in different surface conditions, which implies a semiquantitative connection between the THz emission and the surface band bending with the surface dipoles. Laser-induced THz emission spectroscopy is a promising method for evaluating local surface properties on a wafer scale.

RD53B Wafer Testing for the ATLAS ITk Pixel Detector

RD53B/ITkPix-V1 is the most recent hybrid pixel readout chip development for the ATLAS pixel detector at the HL-LHC. It is the first full-scale 65 nm hybrid pixel-readout chip of its kind. ITkPix-V1 consists of more than one billion transistors with a high memory triplication ratio to cope with the high particle density at the heart of ATLAS. Chips will be as close to the interaction point as possible to optimize the resolution of impact parameters. The ITkPix-V1 chip features a 5-Gbit connection, with special data compression to deal with high hit intensities. In addition, a low-power, low-noise analog front-end is used to ensure high readout speeds and low detection thresholds. Failure of chips in ATLAS would be problematic. Therefore, a thorough test is necessary before and during production. For this purpose, the Bonn ATLAS group has developed BDAQ53, a fast and versatile simulation and testing environment that allows small and large-scale testing for ITkPix-V1 and its successor chips. This conference note will give an overview of the testing environment while focusing on large-scale wafer testing to evaluate ITkPix-V1’s suitability for its deployment at the HL-LHC.

Heterogeneously integrated membrane III-V compound semiconductor devices with silicon photonics platform

Silicon photonics is a key technology for constructing large-scale photonic integrated circuits (PICs) because it enables large-scale wafer processes with high uniformity and quality. To further improve device characteristics, heterogeneous integration of III-V compound semiconductors that provide optical gain, a high modulation efficiency, and optical non-linearity is desired. This paper describes the heterogeneous integration of membrane III-V compound semiconductor photonic devices that have a similar structure including thickness and refractive index. These devices provide efficient optical coupling with a Si waveguide using a simple taper waveguide structure. If the total thickness of the film structure is designed to be less than the critical thickness (calculated to be 430 nm for fabrication conditions such as bonding and growth temperatures), high-quality epitaxial layers can be grown on a thin InP layer directly bonded to the Si substrate. Therefore, regrowth techniques are employed on bonded InP layer on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si substrate. We fabricate two kinds of laser-integrated Mach-Zehnder modulators using epitaxial regrowth on Si substrates. One uses Si phase modulators, and the other uses InP-based modulators. A micro-transfer-printing technology is also important when the number of III-V devices is relatively small. Furthermore, the micro-transfer-printing technology enables devices to be selected that meet the required characteristics before integration. For this purpose, we try to integrate a membrane laser on a Si substrate, in which the membrane laser is fabricated on InP substrate. The device shows a threshold current of 0.8 mA when the active region length is 140 μm. Finally, we briefly describe a transmission module, in which directly modulated membrane lasers and electronic drivers are integrated by flip-chip bonding through Au bumps. To reduce power consumption, it is important to design driver circuits that incorporate semiconductor lasers as electronic components. We demonstrate a 2-channel 53-Gbit/s 4-level pulse amplitude modulation (PAM4) transmitter front-end consisting of a 2-channel PAM4 shunt laser driver and 2-channel O-band directly modulated membrane lasers. The total power consumption is only 60.7 mW, resulting in 0.57 mW/Gbit/s.

A novel circle center location method for a large-scale wafer

The high-precision circle center location of a wafer can implement the automatic acquisition of the special die, which is one of the most significant steps in wafer surface defect detection. Due to the larger scale of the wafer and the smaller field of view of the camera, the circular arc edge captured is an approximate line segment and has less arc information. The existing methods are mainly used to locate the circle center of the full or more than half of the circular arc captured by a large field of view camera, and it is extremely difficult to accurately locate the circle center of the wafer. To solve this problem, we propose a novel circle center location method for the large-scale wafer. A method for measuring the system angle in the horizontal plane by calibration is presented. Throughthe analysis of multiple error sources and the compensation of systemangle, the system angle inthe horizontal plane is the main source of error that causes the positioningerror of the inspection system. Based on the distance constraint and the system angle compensation in the horizontal plane, the edge point set coordinates of multi-segment circular arc images are accurately extracted and transformed in the reference coordinate system. A new hierarchical Bayesian model, which takes the initial circle parameter obtained by an improved method as a priori constraint, is utilized to accurately estimate the circle center and radius of the wafer. The effectiveness of the proposed method is verified by various experiments, which are conducted with real 8-inch and 12-inch wafers using the inspection equipment developed.

Effect of nonvertical ion bombardment due to edge effects on polymer surface morphology evolution and etching uniformity

Maintaining uniform sample etching during a plasma process is a critical requirement for applications in large-scale wafer processing. The interface between the plasma and the sample surface is defined by the plasma sheath, which accelerates ions toward the sample surface. In areas where the plasma sheath is not parallel to the sample surface, such as near the sample edges, the incident ions arrive at shallower, off-normal angles that can result in a greater etch yield relative to other areas of the sample. This phenomenon leads to nonuniform etching, along with characteristic surface morphology evolution. In this work, we utilized a combination of spatial ellipsometry for etching behavior, atomic force microscopy (AFM) for surface morphology evolution, and power spectral density (PSD) analysis to quantify the extent and spatial dependence of the nonuniform etching near the sample edges. The spatial ellipsometry indicated that a region extending for about 1000 μm from the sample edge experiences approximately 10%–15% more thickness loss (∼10–15 nm) relative to areas near the center of the sample under the tested processing conditions. Within this area, the greatest rate of change in the sample thickness occurs within 5 Debye lengths or ∼300 μm from the sample edge. Via AFM analysis, we detected the presence of ripple features that are consistent with directional ion impacts caused by deflection of ions from normal incidence on the surface morphology [Merkulov et al., Appl. Phys. Lett. 80, 4816 (2002)] AFM scans performed in two different sample orientations confirmed that the ripple features are oriented perpendicular to the direction of incident ions and propagate along the direction of the incident ions. Correspondingly, the magnitude of surface roughness decreases as the distance from the sample edge increases. The ripple features were quantified via PSD analysis, which found the presence of a greater population of long-wavelength roughness closer to the sample edge. The findings of this study provide insight into the influence of the plasma sheath distortions near sample edges on the extent of nonuniform sample etching and characteristic surface morphology evolution in plasma etching applications.

Qualification Management in Wafer Fabs: Optimization Approach and Simulation-Based Performance Assessment

Machines need to be individually qualified to run lots of certain families in semiconductor wafer fabrication facilities (wafer fabs). A qualification time window that lasts a couple of days is associated with each family and each tool. The time window can be reinitialized with additional qualification effort as needed and can be extended by on-time processing of qualified families. A mixed-integer linear programming formulation is proposed. The objective function takes into account the backlog costs and inventory holding costs. Moreover, it penalizes qualifications. The optimization approach is applied in a rolling horizon setting using a wafer fab simulation model. The demand for a planning window of several periods is derived using feedback from the shop floor. The results of the simulation experiments demonstrate that an appropriate tradeoff between production objectives and performed qualifications can be achieved by an appropriate configuration of the model. Note to Practitioners —In this article, we propose a mathematical programming-based approach to decide when the tools in wafer fabs have to be qualified for a certain family. These decisions have high practical relevance because qualifications are expensive and time-consuming. A dispatching scheme to implement the qualification decisions is designed. The overall approach is assessed in a rolling horizon setting using a simulation model of a large-scale wafer fab. An appropriate tradeoff between production and qualification goals can be achieved using the proposed approach.

Study of Birefringence and Stress Distribution of SiO2 Film Optical Waveguide on Silicon Wafer

Silica waveguide planar lightwave circuit (PLC) technology is driving the broad applications of various functional components to meet the increasing demands of the industry due to its advanced performance in large-scale wafer mass production. Despite the intense research interests in understanding and relaxing the stress causing the optical birefringence, not much research has been devoted to investigating the stress distribution. In this article, the thermal stress, growth-caused stress, and structural stress are comparably studied. The birefringence distribution of a 6 μm-thick SiO2 film from the center to the edge on a 6-inch silicon wafer was measured to be 0.0006 to 0.0038, leading to an equivalent stress distribution cross the wafer from −170 to −1000 MPa. This implies that the compressive stress of the thick SiO2 film on the wafer was nonuniformly distributed; however, it gradually increased from the center to the edge. Meanwhile, the measured stress of a SiO2 film decreased with the flow rate of the doped GeH4 gas. The algebraic sum of the above three stresses reached excellent agreement with the measurement results in both distribution form and amplitude. In both research and production, the agreeable optical property distributions between the theoretical calculations and experimental measurements are more sustainable to further improving the yields of SiO2 thick film PLC products.

SiO2 passivation layer grown by liquid phase deposition for silicon solar cell application

Surface passivation is one of the primary requirements for high efficient silicon solar cells. Though the current existed passivation techniques are effective, expensive equipments are required. In this paper, a comprehensive understanding of the SiO2 passivation layer grown by liquid phase deposition (LPD) was presented, which was cost-effective and very simple. It was found that the post-annealing process could significantly enhance the passivation effect of the LPD SiO2 film. Besides, it was revealed that both chemical passivation and field-effect passivation mechanisms played important roles in outstanding passivation effect of the LPD SiO2 film through analyzing the minority carrier lifetime and the surface recombination velocity of n-type and p-type silicon wafers. Although the deposition parameters had little influence on the passivation effect, they affected the deposition rate. Therefore, appropriate deposition parameters should be carefully chosen based on the compromise of the deposition rate and fabrication cost. By utilizing the LPD SiO2 film as surface passivation layer, a 19.5%-efficient silicon solar cell on a large-scale wafer (156 mm × 156 mm) was fabricated.

Strip-loaded waveguide-based optical phase shifter for high-efficiency silicon optical modulators

We propose a novel silicon optical phase shifter structure based on heterogeneous strip-loaded waveguides on a photonic silicon on insulator (SOI) platform. The features of an etchless SOI layer and loaded strip would enhance the performance and uniformity of silicon optical modulators on a large-scale wafer. We implemented the phase shifter by loading an amorphous silicon strip onto an SOI layer with a vertical PN diode structure. Compared to the conventional lateral PN phase shifter based on half-etched rib waveguides, this phase shifter shows a >1.5 times enhancement of modulation efficiency and provides >20 GHz high-speed operation.

Large Format Surface-Enhanced Raman Spectroscopy Substrate Optimized for Enhancement and Uniformity.

Gratings have been widely investigated both theoretically and experimentally as surface-enhanced Raman spectroscopy (SERS) substrates, exhibiting, under appropriate circumstances, increased far-field extinctions and near-field intensities over those of an appropriately equivalent number of isolated particles. When the grating order transitions from evanescent to radiative, narrow resonance peaks are observed in the extinction spectrum whose properties can be manipulated by controlling the grating's geometric parameters. Here we report the application of the architectural principles of grating fabrication using a square two-dimensional array of gold-coated nanostructures that achieves SERS enhancements of 10(7) uniformly over areas of square centimeters. The high-performance grating substrates were fabricated using commonly available foundry-based techniques that have been chosen for their applicability to large-scale wafer processing. Additionally, we restricted ourselves to a parametric regime that optimizes SERS performance in a repeatable and reproducible manner.

Incorporating engineering process improvement activities into production planning formulations using a large-scale wafer fab model

In most semiconductor wafer fabrication facilities (wafer fabs), both production and engineering lots share the same expensive equipment. Production lots will be shipped to customers whereas engineering lots are used to support production and process development efforts. While production activities might lead to large revenue, engineering activities result in increased future output. In the present paper, we propose three different production planning formulations. The first formulation assumes a reduced available capacity for production due to engineering activities. Costs for production products are minimised. The second formulation is based on the idea that aggregated demand is available for engineering activities for the entire planning window. Costs for production and engineering products are minimised. Learning effects are incorporated to model the capacity increase due to engineering activities. The third model assumes that demand information for engineering activities is available only for the first period. In addition to learning effects, forgetting effects are modelled to provide an incentive to plan releases of engineering lots in later periods. Costs for production and engineering products and forgetting effects are minimised. The performance of the production planning models is assessed using a simulation model of a large-scale wafer fab including specific dispatching strategies to deal with production and engineering lots. The simulation results demonstrate that the second model slightly outperforms the third one when a rolling horizon approach is taken, while the second model provides significantly higher profit than the first one.

Simplified Subspaced Regression Network for Identification of Defect Patterns in Semiconductor Wafer Maps

Wafer defects, which are primarily defective chips on a wafer, are of the key challenges facing the semiconductor manufacturing companies, as they could increase the yield losses to hundreds of millions of dollars. Fortunately, these wafer defects leave unique patterns due to their spatial dependence across wafer maps. It is thus possible to identify and predict them in order to find the point of failure in the manufacturing process accurately. This paper introduces a novel simplified subspaced regression framework for the accurate and efficient identification of defect patterns in semiconductor wafer maps. It can achieve a test error comparable to or better than the state-of-the-art machine-learning (ML)-based methods, while maintaining a low computational cost when dealing with large-scale wafer data. The effectiveness and utility of the proposed approach has been demonstrated by our experiments on real wafer defect datasets, achieving detection accuracy of 99.884% and ${{{R}}^{2}}$ of 99.905%, which are far better than those of any existing methods reported in the literature.