Large-scale Silicon Research Articles

Large-Scale and Broadband Silicon Nitride Optical Phased Arrays

Large-scale one-dimensional (1D) waveguide surface grating arrays enable smaller antenna pitches and larger apertures for the OPAs. However, broad wavelength tuning is required for wide-angle beam steering along the transverse θ direction for 1D waveguide antennas. High-resolution and wide-angle beam steerings at visible and NIR wavelengths have not been reported in previous studies. This study presents a large-scale SiNx nanophotonic phased array with an optical aperture of 2.3 mm × 2.3 mm, which is the largest OPA aperture produced in the visible and NIR bands thus far. Broad wavelength tuning from 650 nm to 1064 nm is employed to achieve small beam divergences of 0.03° – 0.054° in a wide steering range of 53.7°. The overall losses are accordingly analyzed with 3 dB bandwidth of 150 nm from 785 nm to 935 nm. Furthermore, with a supercontinuum laser illuminated on the OPA, more than 1000 resolvable spots merge together in the free space and form a fine strip of continuous line in the far-field projection with an FOV of >50°. This study demonstrates both high steering resolution and wide steering angle at wavelengths from visible to NIR on SiNx OPAs for the first time, to the best of our knowledge.

The Design of a Low-Loss, Fast-Response, Metal Thermo-Optic Phase Shifter Based on Coupled-Mode Theory

A thermo-optic phase shifter is of great importance in silicon photonics. However, it is difficult to simultaneously achieve a good performance in insertion loss and in response speed by using traditional thermal tuning through a metallic heater. In this paper, based on coupled-mode theory, we propose a method to place high-loss materials close to the optical waveguide while maintaining the low loss of the optical device, which ensures the low insertion loss (~0.78 dB) of the phase shifter. Additionally, thanks to the very short distance between the rib waveguide and the chromium (Cr) heater, the phase shifter exhibits a high response speed (1.15 μs in rise time and 2.18 μs in decay time) with a measured bandwidth (BW) of 186 kHz. Moreover, we further optimize the structure of phase shifters, leading to the reduction of π-shift power consumption from 25.1 mW to 13.6 mW. Our proposed phase shifters have great potential in large-scale silicon photonic integrated circuits.

Large-Scale Wideband Light-Trapping Black Silicon Textured by Laser Inducing Assisted with Laser Cleaning in Ambient Air.

Black silicon, which is an attractive material due to its optical properties, is prepared mainly by laser inducing in an SF6 atmosphere. Considering the effect of SF6 gas on the environment and human health, here we propose an efficient, economical, and green approach to process large-scale black silicon. In the wavelength range of 0.3–2.5 µm, the role of air could replace SF6 gas to texture black silicon by laser inducing with appropriate processing parameters. Then, to extend the working window of its excellent light-trapping status, laser-plasma shockwave cleaning was introduced to eliminate the deposition and improve the structures and morphology. The results revealed that the micro-nano structures became higher, denser, and more uniform with increasing cleaning times and deteriorating cleaning velocity, which compensated for the role of S atoms from the ambient SF6. Moreover, absorptance above 85% in the wavelength range of 0.3–15 µm was realized using our method. The effect of scanning pitch between adjacent rows on large-scale black silicon was also discussed. Our method realized the ultrahigh absorptance of large-scale black silicon fabricated in air from visible to mid-infrared, which is of significance in the field of optoelectronic devices.

Large-Scale Black Silicon Induced by Femtosecond Laser Assisted With Laser Cleaning

Black silicon is a promising and effective candidate in the field of photoelectric devices due to the high absorptance and broad-spectrum absorption property. The deposition around the processing area induced by the pressure of SF6, gravity, and the block of the processing chamber interferes the adjacent laser ablation and hampers uniform large-scale black silicon fabrication. To solve the problem, femtosecond laser- induced black silicon assisted with laser plasma shockwave cleaning is creatively proposed in our study. The results showed that higher, denser, and more uniform microstructures can be obtained than the conventional laser-induced method without laser cleaning. The average absorptance is 99.15% in the wavelength range of 0.3–2.5 µm, while it is more than 90% in the range of 2.5–20 µm. In addition, the scanning pitch dependence of surface morphology is discussed, and the better result is obtained in the range of 25–35 µm with 40-µm laser spot. Finally, a large-scale 50-mm × 50-mm black silicon with uniform microstructures was prepared by our method. It has been demonstrated that the deposition is effectively eliminated via our method, and the optical absorption is also enhanced significantly. It is of great significance for realizing large-scale preparation of photoelectric devices based on black silicon and lays the foundation for the development of laser-inducing equipment and industrial application.

Automated visual inspection and defect detection of large-scale silicon strip sensors

For the Phase-II Upgrade of the ATLAS Detector, the Inner Detector will be replaced with the Inner Tracker (ITk), consisting of a pixel and a strip tracker. The 17,888 silicon strip detector modules comprising the ITk strip tracker will be assembled from silicon strip sensors and flexes with readout chips in a manual assembly process performed at 20 module assembly sites in a complex distribution chain, which requires quality control steps to be performed after each distribution and assembly step. Sensor quality control requires a visual inspection of the full sensor area (about 100 cm2) of each sensor to detect and log any defects (e.g. scratches, breakdown areas or chipped corners) or contamination. Since manual surveys of full sensor areas for several thousand sensors are both time-consuming and prone to errors, alternative methods were investigated to automate the process and improve its reliability. This paper presents a setup developed to take high-resolution images of full silicon strip sensors with high repeatability quickly and an algorithm developed for the automated detection of defects, built using functions and filters from popular open-source visual processing packages OpenCV and Scikit-image. Methods were developed both for small-scale high-resolution images and full-size sensor images with lower resolution — both are presented here.

Low-loss erbium-incorporated rare-earth oxide waveguides on Si with bound states in the continuum and the large optical signal enhancement in them

Integrated optical amplifiers are essential building blocks for emerging applications of large-scale and complex silicon photonic integrated circuits. Single-crystal erbium-incorporated rare-earth oxide thin films epitaxially grown on silicon substrate could be a promising material candidate. Based on the mechanism of bound states in the continuum, we have developed a low-loss waveguide platform for such materials. The waveguides are formed by patterning a silicon nitride cap layer grown on a rare-earth oxide thin film on silicon-on-insulator substrate. Low propagation loss of 4.70 dB/cm has been obtained in waveguides with silicon nitride/rare-earth oxide/silicon layer stack thickness of 72 nm/90 nm/300 nm, width of 1.08 µm, at a wavelength of 1445.8 nm. Optical signal enhancement in these waveguides upon optical pumping has been observed in a wide wavelength range of 1510 to 1560 nm, with a large peak enhancement of ∼16 dB/cm around 1536 nm. Our results represent an important step towards the realization of high-performance monolithic-integrated optical amplifiers on Si.

Wafer-Scale Electroactive Nanoporous Silicon: Large and Fully Reversible Electrochemo-Mechanical Actuation in Aqueous Electrolytes.

Nanoporosity in silicon results in interface-dominated mechanics, fluidics, and photonics that are often superior to the ones of the bulk material. However, their active control, for example, by electronic stimuli, is challenging due to the absence of intrinsic piezoelectricity in the base material. Here, for large-scale nanoporous silicon cantilevers wetted by aqueous electrolytes, electrosorption-induced mechanical stress generation of up to 600 kPa that is reversible and adjustable at will by potential variations of ≈1 V is shown. Laser cantilever bending experiments in combination with in operando voltammetry and step coulombmetry allow this large electro-actuation to be traced to the concerted action of 100 billions of parallel nanopores per square centimeter cross-section and determination of the capacitive charge-stress coupling parameter upon ion adsorption and desorption as well as the intimately related stress actuation dynamics for perchloric and isotonic saline solutions. A comparison with planar silicon surfaces reveals mechanistic insights on the observed electrocapillarity (Hellmann-Feynman interactions) with respect to the importance of oxide formation and wall roughness on the single-nanopore scale. The observation of robust electrochemo-mechanical actuation in a mainstream semiconductor with wafer-scale, self-organized nanoporosity opens up novel opportunities for on-chip integrated stress generation and actuorics at exceptionally low operationvoltages.

Thermally enhanced responsivity in an all-silicon optical power monitor based on defect-mediated absorption

We demonstrate a high responsivity all-silicon in-line optical power monitor by using the thermal effect to enhance the quantum efficiency of defect-mediated absorption at 1550 nm. The doping compensation technique is utilized to increase the density of lattice defects responsible for the sub-bandgap absorption and suppress the detrimental free carrier absorption. The 200-μm-long device presents a propagation loss as low as 2.9 dB/cm. Its responsivity is enhanced from 12.1 mA/W to 112 mA/W at − 9 V bias by heating the optical absorption region. With this device, we build an optical power monitoring system that operates in the sampling mode. The minimal detectable optical power of the system is below − 22.8 dBm , while the average power consumption is less than 1 mW at a sampling frequency of 10 Hz. Advantages of this scheme in terms of high responsivity, low insertion loss, and low power consumption lend itself to implement the feedback control of advanced large-scale silicon photonic integrated circuits.

Suspended AlGaAs waveguide for integrated nonlinear photonics

AlxGa1-xAs compound is one of the promising platforms to realize high performance nonlinear optical devices, which provide ultra-high third order nonlinearity and negligible two-photon absorption in the range of telecom wavelength. To achieve highly efficient optical confinement, the conventional AlGaAs waveguide cladding layer is achieved by using SiO2 via the wafer bonding process or AlGaAs with higher Al concentration, which requires a complex fabrication process. In this work, we demonstrate a suspended Al0.5Ga0.5As waveguide structure directly grown on the GaAs substrate by using the molecular beam epitaxy system. Both self-phase modulation and four-wave-mixing experiments are performed. By solving the nonlinear Schrödinger equations and the degenerated parametric amplification process, the n2 value is calculated to be 1.6 × 10−17 m2/W, and the nonlinear parameter is determined to be 155 W−1 m−1. As the AlGaAs thin film can be directly grown on the Si based substrate, this suspended waveguide platform could potentially be developed on a large scale silicon wafer for integrated nonlinear photonic devices.

Radiation tolerant, thin, passive CMOS sensors read out with the RD53A chip

The radiation hardness of passive CMOS pixel sensors fabricated in 150nm LFoundry technology is investigated. CMOS process lines are especially of interest for large-scale silicon detectors as they offer high production throughput at comparatively low cost. Moreover, several features like poly-silicon resistors, MIM-capacitors and several metal layers are available which can help enhance the sensor design. The performance of a 100µm thin passive CMOS sensor with a pixel pitch of 50µm at different irradiation levels, 5 × 1015neqcm−2 and 1 × 1016neqcm−2, is presented. The sensor was bump-bonded and read out using the RD53A readout chip. After the highest fluence a hit-detection efficiency larger than 99% is measured for minimum ionising particles. The measured equivalent noise charge is comparable to conventional planar pixel sensors. Passive CMOS sensors are thus an attractive option for silicon detectors operating in radiation harsh environments like the upgrades for the LHC experiments.

Theoretical and experimental study on epitaxial growth of antiphase boundary free GaAs on hydrogenated on-axis Si(001) surfaces

The formation of double-layer atomic steps on Si(001) surfaces is an efficient way to eliminate the antiphase boundaries (APBs) on GaAs/Si(001) interfaces. The surface energy of on-axis Si(001) surfaces with different atomic step structures was calculated and analyzed from the first principles. An optimal hydrogen-annealing process condition, the hydrogen pressure of 800 mbar and the annealing temperature of 800 °C for 10 min, was obtained experimentally. Under this annealing condition, a 420 nm APB-free GaAs epitaxial layer grown on on-axis Si(001) substrates was achieved by metal-organic chemical vapor deposition. The effect of the annealing temperature on the APB density of the GaAs/Si(001) samples was explained from the aspects of thermodynamics and kinetics. It is of great significance to optimize the growth conditions of APB-free III–V epitaxial materials on on-axis Si(001) surfaces for the large-scale silicon monolithic integration of optoelectronic devices.

Nanoscale directional etching features and mechanism of HF/HNO3 etchant

Large-scale and periodic silicon nanostructure arrays are an essential component for various functional devices. However, the conventional selective etching mechanism of specific crystal faces for monocrystalline silicon generally achieves slope or vertical morphology, which greatly limits the preparation of other morphology of silicon nanostructures. In this work, the conventional isotropic etchant HF/HNO3 has successfully achieved nanoscale directional etching and cambered morphology on monocrystalline silicon surface for the first time by changing the synchronous process of oxidation and dissolution into an asynchronous process. Based on the self-assembled monolayer colloidal crystal templates, large-area and high-quality nanopore arrays are prepared on the monocrystalline silicon surface. Particularly, the directional etching ability of HF/HNO3 etchant is further confirmed by combining with electron beam lithography and scanning probe lithography technologies. Hence, this nanoscale directional etching mechanism and etchants provide a promising strategy to achieve cambered morphology nanopores on the monocrystalline silicon surface.

Length prediction of silicon nanowires (SiNWs) prepared by the MACE method using the ANN-COA-PSO algorithm for high supercapacitor applications

In this study, the metal-assisted chemical etching of silicon with the help of metal is used to fabricate large-scale silicon nanowire arrays (SiNWs). This method was optimised by artificial neural networks (ANN) and the cuckoo optimization algorithm (COA) was used to optimize ANN. Finally, the particle swarm optimization (PSO) method has been used to achieve the maximum length of silicon nanowires. As a result, the nanowires produced by the 1 M NaOH electrolyte had the properties of a capacitive cloud with a capacity of 758 mF/cm2. It has the potential to be an excellent candidate for supercapacitor applications.

Fabrication of 2D silicon nano-mold by side etch lift-off method

Nano-imprint technology is a method of nano-pattern reproduction, has the characteristics of high resolution, high throughput, and low-cost. It can reduce the complexity and cost of the equipment while improving the resolution, which considered a promising industrial production technology. The key to nanoimprinting lies in the mold, and the quality of the mold directly determines the quality of the imprinted graphics. Here, a method for fabricating sub-100 nm concave 2D silicon nano-mold by side etch lift-off is proposed. The effects of different wet etching time and the metal deposition angle on the width of nanochannels were studied. The measurement result of dry etching shows that on the entire 4 inch silicon wafer, the width of the nanochannel varies by 4% and the depth by 2%. The width of the nanochannel between chips varies by 0.7%, and the depth variation is 1%. With this new method, high-precision and large-scale silicon nano-mold can be produced, which has great potential for realizing high-precision and low-cost manufacturing of nano devices.

Improvement of critical temperature of niobium nitride deposited on 8-inch silicon wafers thanks to an AlN buffer layer

In this paper, we study the crystalline properties and superconducting critical temperature of ultra-thin (5–9 nm) NbN films deposited on 8-inch silicon wafers by reactive sputtering. We show that the deposition of NbN on a thin (10–20 nm) AlN buffer layer, also synthesized by reactive sputtering, improves the critical temperature by several Kelvin, up to 10 K for 9 nm NbN on 20 nm AlN. We correlate this improvement to the higher-crystalline quality of NbN on AlN. While NbN deposited directly on silicon is polycrystalline with randomly oriented grains, NbN on AlN(0001) is textured along (111), due to the close lattice match. The superconducting properties of the NbN/AlN stack are validated by the demonstration of fibre-coupled normal-incidence superconducting nanowire single photon detectors. The whole fabrication process is CMOS compatible, with a thermal budget compatible with the integration of other passive and active components on silicon. These results pave the way for the integration of a large number of surface or waveguide-integrated detectors on large-scale silicon wafers. Furthermore, as AlN is transparent over a broad wavelength range from the visible to the near-infrared, the optimized superconducting NbN/AlN stack can be used for a wide variety of applications, from imaging to quantum communications and quantum computing.

Pauli Blockade in Silicon Quantum Dots with Spin-Orbit Control

Quantum computation relies on accurate measurements of qubits not only for reading the output of the calculation, but also to perform error correction. Most proposed scalable silicon architectures utilize Pauli blockade of triplet states for spin-to-charge conversion. In recent experiments there have been instances when instead of conventional triplet blockade readout, Pauli blockade is sustained only between parallel spin configurations, with |T0⟩ relaxing quickly to the singlet state and leaving |T+⟩ and |T−⟩ states blockaded—which we call parity readout. Both types of blockade can be used for readout in quantum computing, but it is crucial to maximize the fidelity and understand in which regime the system operates. We devise and perform an experiment in which the crossover between parity and singlet-triplet readout can be identified by investigating the underlying physics of the |T0⟩ relaxation rate. This rate is tunable over 4 orders of magnitude by controlling the Zeeman energy difference between the dots induced by spin-orbit coupling, which in turn depends on the direction of the applied magnetic field. We suggest a theoretical model incorporating charge noise and relaxation effects that explains quantitatively our results. Investigating the model both analytically and numerically, we identify strategies to obtain on demand either singlet-triplet or parity readout consistently across large arrays of dots. We also discuss how parity readout can be used to perform full two-qubit state tomography and its impact on quantum error-detection schemes in large-scale silicon quantum computers.Received 22 April 2020Revised 2 June 2020Accepted 3 December 2020DOI:https://doi.org/10.1103/PRXQuantum.2.010303Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.Published by the American Physical SocietyPhysics Subject Headings (PhySH)Research AreasQuantum computationQuantum tomographyPhysical SystemsQuantum dotsSemiconductorsQuantum InformationCondensed Matter & Materials Physics

Analysis of Scale-up Parameters in 3D Silicon-Nanowire Lithium-Battery Anodes

New, higher-capacity materials are required in order to address the growing need for batteries with greater energy density and longer cycle life for modern applications. We present here a study of silicon-nanowires (SiNWs) anodes, synthesized via a novel, catalysts free and scalable chemical vapor deposition (CVD) on stainless-steel mesh[1]. Our study is focused on the adaptation of the SiNWs anode in various large-scale configurations. Our research efforts have resulted in the successful scale-up of the silicon anode from Si/Li half-cells with areal capacity of 14mAh/cm2, to coin cells with commercial cathodes, industrial 1/3AAA cells and eventually multilayered pouch cells. Testing of the anodes in industrial cells demonstrated the applicability of these anodes in commercial lithium-ion batteries that can run for hundreds of cycles, withstanding fast charge and discharge and subzero temperatures. An all-solid Si/polymer electrolyte/NCA cell was also demonstrated as a proof of concept (POC). We assign the major degradation mechanism of the SiNWs anodes to the growth of the primary and secondary SEI thickness and impedance during cycling. We found that the depth of lithiation/delithiation and the voltage profile of the cell significantly affect cell's stability[2].Figure 1- a) SiNWs anode grown on SS mesh, b) cycle life of 1Ah pouch cell with a 5.5mgSi/cm2 anode References[1] N. Harpak, G. Davidi, D. Schneier, S. Menkin, E. Mados, D. Golodnitsky, E. Peled, F. Patolsky, Large-Scale Self-Catalyzed Spongelike Silicon Nano-Network-Based 3D Anodes for High-Capacity Lithium-Ion Batteries, Nano Lett. (2019) acs.nanolett.8b05127. doi:10.1021/acs.nanolett.8b05127.[2] D. Schneier, N. Harpak, S. Menkin, G. Davidi, M. Goor, E. Mados, G. Ardel, F. Patolsky, D. Golodnitsky, E. Peled, Analysis of Scale-up Parameters in 3D Silicon-Nanowire Lithium-Battery Anodes Analysis of Scale-up Parameters in 3D Silicon-Nanowire Lithium- Battery Anodes, (2020). doi:10.1149/1945-7111/ab6f5a. Figure 1

Scaling capacity of fiber-optic transmission systems via silicon photonics

AbstractThe tremendous growth of data traffic has spurred a rapid evolution of optical communications for a higher data transmission capacity. Next-generation fiber-optic communication systems will require dramatically increased complexity that cannot be obtained using discrete components. In this context, silicon photonics is quickly maturing. Capable of manipulating electrons and photons on the same platform, this disruptive technology promises to cram more complexity on a single chip, leading to orders-of-magnitude reduction of integrated photonic systems in size, energy, and cost. This paper provides a system perspective and reviews recent progress in silicon photonics probing all dimensions of light to scale the capacity of fiber-optic networks toward terabits-per-second per optical interface and petabits-per-second per transmission link. Firstly, we overview fundamentals and the evolving trends of silicon photonic fabrication process. Then, we focus on recent progress in silicon coherent optical transceivers. Further scaling the system capacity requires multiplexing techniques in all the dimensions of light: wavelength, polarization, and space, for which we have seen impressive demonstrations of on-chip functionalities such as polarization diversity circuits and wavelength- and space-division multiplexers. Despite these advances, large-scale silicon photonic integrated circuits incorporating a variety of active and passive functionalities still face considerable challenges, many of which will eventually be addressed as the technology continues evolving with the entire ecosystem at a fast pace.

1.3-µm passively mode-locked quantum dot lasers epitaxially grown on silicon: gain properties and optical feedback stabilization

This work reports on an investigation of the optical feedback in an InAs/InGaAs passively mode-locked quantum dot (QD) laser epitaxially grown on silicon. Under the stably-resonant optical feedback condition, experiments demonstrate that the radio-frequency linewidth is narrowed whatever the bias voltage applied on the saturable absorber (SA) is; on the other hand, the effective linewidth enhancement factor of the device increases with the reverse bias voltage on the SA, hence it is observed that such an increase influences the mode-locking dynamic and the stability of device under optical feedback. This work gives insights for stabilizing epitaxial QD mode-locked lasers on silicon which is meaningful for their applications in future large-scale silicon electronic and photonic applications requiring low power consumption as well as for high-speed photonic analog-to-digital conversion, intrachip/interchip optical clock distribution and recovery.

Low-Loss and Broadband Silicon Photonic 3-dB Power Splitter with Enhanced Coupling of Shallow-Etched Rib Waveguides

A silicon photonic 3-dB power splitter is one of the essential components to demonstrate large-scale silicon photonic integrated circuits (PICs), and can be utilized to implement modulators, 1 × 2 switches, and 1 × N power splitters for various PIC applications. In this paper, we reported the design and experimental demonstration of low-loss and broadband silicon photonic 3-dB power splitters. The power splitter was realized by adiabatically tapered rib waveguides with 60-nm shallow etches. The shallow-etched rib waveguides offered strong coupling and relaxed critical dimensions (a taper tip width of 200 nm and gap spacing of 300 nm). The fabricated device exhibited an excess loss as low as 0.06 dB at a 1550-nm wavelength and a broad operating wavelength range from 1470 nm to 1570 nm. The relaxed critical dimensions (≥200 nm) make the power splitter compatible with standard fabrication processes of existing silicon photonics foundries.