Large Scale Integrated Circuit Processing Research Articles

Fabrication Method of Sub-100 nm Metal–Oxide–Semiconductor Field-Effect Transistor with Thick Gate Oxide

Based on the standard large-scale integrated circuit (LSI) process, sub-100 nm gate metal–oxide–semiconductor field-effect transistor (MOSFET) with thick gate oxide was fabricated. This was realized only by the modification of layout design, and no customization of the fabrication process was necessary. This unique designing technique is of great use in obtaining low-input-leakage MOSFET by advanced LSI process for high-performance analog applications.

The Impacts of Back-End High Temperature Thermal Treatments on the Characteristics and Gate Oxide Reliability of Thin Film Transistor in Ultra Large Scale Integrated Circuit Process

The impacts of the two major high temperature treatments on the characteristics of thin film transistors (TFT's) in the back-end process of ultra large scale integrated circuit (ULSI) technology have been investigated. TFT's without any high temperature treatment show poor characteristics. High temperature furnace annealing and rapid thermal annealing (RTA) which are performed for boron phosphorous tetra ethyl ortho silicate (BPTEOS) planarization can improve the characteristics of low temperature recrystallized TFT. Then, the technologies used for contact annealing result significant difference on the characteristics of TFT's. High temperature furnace contact annealing can still greatly improve the characteristics of TFT's. However, after furnace annealing for BPTEOS planarization, RTA contact annealing deteriorates the characteristics of TFT. High temperature furnace annealing for BPTEOS planarization improves the charge to breakdown (Q bd) value of the gate oxide of TFT and so does the furnace contact annealing. However, RTA contact annealing performed after the furnace planarization flow deteriorates that of the gate oxide.

Fabrication of arrayed glassy carbon field emitters

Glassy carbon has desirable properties for electron field emission such as surface inertness, electrical conductivity, and thermal stability. In addition, a uniform thick substrate with a polished surface is easily obtainable. This enables one to apply large scale integrated circuit processing for fabricating arrayed tips. By using oxygen reactive ion etching, cusps over 3.5 μm in height and 2.5 μm in base diameter are fabricated with a tip radius of under 10 nm. The process is assisted by the formation of a layer of etch products which protects the newly forming tip from bending and over etching. The field emission current up to 50 μA from the glassy carbon tips is obtained by applying high voltage to a mesh anode. The current which passed through the mesh anode is collected at another electrode and measured. The Fowler–Nordheim plot suggests the existence of nm scale structure on the tip. This favorable result indicates glassy carbon substrate is a good substrate for field emitter arrays.

Contactless optical evaluation of processing effects on carrier lifetime in silicon

Contactless, optical modulation of free-carrier absorption has been used to identify minority-carrier lifetime degradation associated with both novel and common very large scale integrated circuit processing steps in p-type silicon wafers. Carrier lifetime degradation and a corresponding increase in surface recombination velocity was found to be associated with the silicon etchants ethylenediamine-pyrocatechol-water (EDP) and potassium hydroxide (KOH), prolonged exposure to hydrofluoric acid (HF and BHF), and ion bombardment associated with a variety of plasma etching steps. Knowledge of process-induced lifetime degradation obtained by this technique may offer significant input into the development of high-yield very large scale integrated circuit processes.