Large-scale Circuits Research Articles

Microbead Encapsulation for Protection of Electronic Components

Abstract This study investigates the application of microbeads as an innovative encapsulation technique to protect electronic components from harsh mechanical strain. Traditional encapsulation methods using hard epoxy provide substantial mechanical support but create thermal expansion mismatch issues, potentially leading to electronic component failure. We explore the use of finely powdered microbeads to achieve protective structures combining stiffness and energy absorption. The research focuses on key variables, including microbead size, microbead roughness, compaction of microbeads, and circuit board mounting in the encapsulation, all of which influence the encapsulation's effectiveness. Experimental setups and testing protocols were developed to assess the performance of various microbead materials under different impact conditions. Results demonstrate that microbead encapsulation significantly reduces strain on circuit boards, minimizing the risk of damage during mechanical shocks. However, challenges remain, such as optimizing microbead characteristics and modeling their behavior within large-scale circuit board assemblies. Despite these challenges, the findings suggest that microbead encapsulation offers a promising alternative to conventional methods, enhancing the durability and reliability of electronic components in high-stress environments.

Revealing excitation-inhibition imbalance in Alzheimer’s disease using multiscale neural model inversion of resting-state functional MRI

BackgroundAlzheimer’s disease (AD) is a serious neurodegenerative disorder without a clear understanding of pathophysiology. Recent experimental data have suggested neuronal excitation-inhibition (E-I) imbalance as an essential element of AD pathology, but E-I imbalance has not been systematically mapped out for either local or large-scale neuronal circuits in AD, precluding precise targeting of E-I imbalance in AD treatment.MethodIn this work, we apply a Multiscale Neural Model Inversion (MNMI) framework to the resting-state functional MRI data from the Alzheimer’s Disease Neuroimaging Initiative (ADNI) to identify brain regions with disrupted E-I balance in a large network during AD progression.ResultsWe observe that both intra-regional and inter-regional E-I balance is progressively disrupted from cognitively normal individuals, to mild cognitive impairment (MCI) and to AD. Also, we find that local inhibitory connections are more significantly impaired than excitatory ones and the strengths of most connections are reduced in MCI and AD, leading to gradual decoupling of neural populations. Moreover, we reveal a core AD network comprised mainly of limbic and cingulate regions. These brain regions exhibit consistent E-I alterations across MCI and AD, and thus may represent important AD biomarkers and therapeutic targets. Lastly, the E-I balance of multiple brain regions in the core AD network is found to be significantly correlated with the cognitive test score.ConclusionsOur study constitutes an important attempt to delineate E-I imbalance in large-scale neuronal circuits during AD progression, which may facilitate the development of new treatment paradigms to restore physiological E-I balance in AD.

The Analysis of Applications of Microcomputers in Information Engineering: From Automatic Control Electromechanical Systems to LSI Circuit Design

This paper explores the significant developments in computer technology within the field of information engineering, with a particular focus on the applications of microcomputers. The research delves into two key areas: automatic control electromechanical systems and large-scale integrated circuits (LSI). In recent years, the integration of microcomputers in these systems has transformed the way data is processed, improving system efficiency and precision. The literature review identifies advancements in microcomputer-based control systems, which enhance real-time responsiveness and system stability, alongside innovations in circuit design that contribute to higher integration density and reduced power consumption. Case studies further highlight practical applications in industrial automation and GPS receiver design, demonstrating how microcomputers optimize both functionality and energy efficiency. By synthesizing these findings, this paper underscores the critical role of microcomputers in advancing modern information engineering and offers recommendations for future research, especially in areas where artificial intelligence and edge computing are integrated into next-generation systems. This study contributes to the understanding of how microcomputers enhance technological efficiency and drive innovation in complex engineering environments

Integration of partially observed multimodal and multiscale neural signals for estimating a neural circuit using dynamic causal modeling.

Integrating multiscale, multimodal neuroimaging data is essential for a comprehensive understanding of neural circuits. However, this is challenging due to the inherent trade-offs between spatial coverage and resolution in each modality, necessitating a computational strategy that combines modality-specific information effectively. This study introduces a dynamic causal modeling (DCM) framework designed to address the challenge of combining partially observed, multiscale signals across a larger-scale neural circuit by employing a shared neural state model with modality-specific observation models. The proposed method achieves robust circuit inference by iteratively integrating parameter estimates from local microscale and global meso- or macroscale circuits, derived from signals across various scales and modalities. Parameters estimated from high-resolution data within specific regions inform global circuit estimation by constraining neural properties in unobserved regions, while large-scale circuit data help elucidate detailed local circuitry. Using a virtual ground truth system, we validated the method across diverse experimental settings, combining calcium imaging (CaI), voltage-sensitive dye imaging (VSDI), and blood-oxygen-level-dependent (BOLD) signals-each with distinct coverage and resolution. Our reciprocal and iterative parameter estimation approach markedly improves the accuracy of neural property and connectivity estimates compared to traditional one-step estimation methods. This iterative integration of local and global parameters presents a reliable approach to inferring extensive, complex neural circuits from partially observed, multimodal, and multiscale data, showcasing how information from different scales reciprocally enhances entire circuit parameter estimation.

Preparation of Slurry for Tape Casting of AlN Ceramic Substrates

AlN ceramics are employed in a multitude of applications including large-scale integrated circuit (LIC) packaging substrates, electrostatic chucks, and transparent ceramics due to their excellent thermal conductivity, insulation and dielectric properties, robust corrosion resistance, and thermal expansion coefficient nearly identical to that of silicon. Tape casting is the optimal methodology for the fabrication of large-area, thin, and flat ceramics and components. However, the well-dispersed slurry with high solid loading is required to obtained the ceramic substrates with excellent properties by tape casting. Therefore, in this study, the effects of dispersant content, first ball milling time, binder content, and R value (plasticizer/binder) on the rheological properties of aluminum nitride slurry and casted sheet qualities were investigated. The results indicated that the optimal dispersant formulation was 1.1 wt%, the binder formulation was 2 wt%, the R value was 1.5, and the solid content was 60 wt%. The utilization of the aforementioned organic system enabled the preparation of AlN sheet exhibiting favorable morphology, high solid content, and flexibility.

Scheme for a bidirectionally pumped quantum light source on a silicon chip.

Large-scale quantum photonic circuits require integrating multiple single-photon sources, which are typically based on spontaneous four-wave mixing (SFWM) in spiral waveguides or microring resonators (MRRs). Photons can be generated in both clockwise (CW) and counterclockwise (CCW) orientations from a single source in a Sagnac configuration, showing promise for improving scalability. In this work, we propose a fully integrable scheme for bidirectional creation and usage of single photons. This concept is based on two asymmetric Mach-Zehnder interferometers (AMZIs) integrated within the Sagnac loop. As a proof of concept, we fabricated a device with a spiral waveguide on a silicon chip and demonstrated its application as a quantum splitter and two multi-wavelength quantum light sources.

Designing New Ultra-Radiopure, High-Strength Electroformed CuCr Alloys, for Rare Event Searches

Immense progress has been achieved in understanding the Cosmos over more than 45 orders of magnitude in length. Alas, fundamental questions remain about the nature of; a) Dark Matter (DM); and b) neutrinos. DM’s existence, corresponding to 84.5% of the Universe’s matter, is established via astrophysical observations and precise measurements. Several search approaches have been employed, but “direct detection” is the most prominent: aiming to observe DM from the Milky Way halo via its coherent elastic scattering off a nucleus.Copper is the material of choice for rare event searches: it can be procured commercially at low cost and high purity, and it has no long lifetime isotopes. Alas, it may be contaminated during manufacturing and can be activated by fast neutrons from cosmic rays. In an effort to achieve even higher radiopurity, attention is focused on electroformed copper (EFCu), which has favorable radiochemical, thermal, and electrical properties. To fulfil the unique radiopurity requirements, experiments pioneer large-scale additive-free Cu electroformation, e.g. the on-going project ECUME. This novel technique [1] leads to extreme radiopurities with contamination below 10- 14 grams of 232Th and 238U per Cu gram. However, Copper is highly ductile and of low strength, limiting its use for moving mechanical, high-pressure, and load-bearing parts. This would improve the capability for experiments such as DarkSPHERE [2], a large-scale fully electroformed underground spherical proportional counter operating under high pressureto probe uncharted territory in the search for DM, and is vital for nEXO', a neutrinoless-double β-decay experiment aiming to clarify the nature of neutrinos.The most promising alloying element for improved strength of EFCu is Chromium (Cr). It has been experimentally demonstrated that small additions of Cr, combined with heat treatment and aging, improve strength by 70% [3]. However, Cr additions lead to impurities, and a compromise between strength and radiopurity is required by exploring a complex parameter space of compositions and strengthening mechanisms [4].Cr solubility in Cu is very limited and small additions of Ti can allow for improved mechanical strengthening due to reinforced precipitation. A critical evaluation of the ternary phase diagram of the Cr-Cu-Ti system is underway to inform the particular parameter space of compositions and strengthening mechanisms within the CALPHAD framework. This system has gained recently significant interest in the development of CuCrTi alloys for contact wires of high-speed, large-scale integrated circuit lead frames and electronic connectors [5].Our work addresses materials challenges by developing high radiopure CuCr and CuCrTi alloys with significantly higher strength compared to Cu. The project will deliver a novel approach based on the Integrated Computational Materials Engineering (ICME) framework enabling rapid design of new, application-specific alloys for fields where thermodynamic and kinetic description of the system are crucial. Electroformation in additive-free bath is the focus of the project, which will push the boundaries in many fields, from fundamental science to industrial applications.

A study of advances in machine learning-based electronic design automation

Abstract. The electronic design automation (EDA) is a convenient tool for designing integrated circuits (IC), which is employed extensively both in academic and engineering. The design of integrated circuits is conducted in accordance with a defined design flow, commonly referred to as the chip design flow, which can be divided into two distinct parts, the front-end design and the back-end design. Following a long period of evolution, the chip design flow of EDA has been gradually improved. Besides, it achieved some accomplishments during this period. However, with the growing demand of ICs, especially Very Large-Scale Integration Circuit (VLSI), the existing EDA is not adequate for the requirement. In addition, the EDA technology has been so developed that it is relatively less flexible. In this context, concerns about the future of EDA have recently emerged. In response to this challenge, research has mentioned that machine learning methods (ML methods) can improve the functionality of EDA. The ML method covers most of steps of EDAs design flow, especially back-end design. The machine learning-based electronic design automation is still in its infancy, which is presented with a multitude of challenges. Therefore, the paper explores the development of EDA by reviewing and organizing the related literature, and summarizes the application of ML methods in EDA, thereby providing the future development trend of ML-based EDA.

An efficient leakage power optimization framework based on reinforcement learning with graph neural network

Threshold voltage (Vth\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$V_{th}$$\\end{document}) assignment is convenient for leakage optimization due to the exponential relation between leakage power and Vth\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$V_{th}$$\\end{document} by swapping logic cells without routing effort. However, it poses great challenge in large scale circuit design as an NP-hard problem. Machine learning-based approaches have been proposed to solve this problem, aiming to achieve well tradeoff between leakage power reduction and runtime speed up without new induced timing violation. In this paper, a leakage power optimization framework based on reinforcement learning (RL) with graph neural network (GNN) is first-ever proposed to formulate Vth\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$V_{th}$$\\end{document} assignment as a RL process by learning timing and physical characteristics of each circuit instance with GNN. Multiple instances are selected in a non-overlapped manner for each RL action iteration to speed up convergence and decouple timing interdependence along circuit path, where the corresponding reward is carefully defined to tradeoff between leakage reduction and potential timing violation. The proposed framework was validated by the Opencores and IWLS 2005 benchmark circuits with TSMC 28 nm technology. Experimental results demonstrate that our work outperforms prior non-analytical and GNN-based methods with better leakage power optimization by additional 5% to 17% reduction, which is highly consistent with the commercial tool. When transferring the trained RL-based framework to unseen circuits, it achieves the roughly identical leakage optimization results as seen circuit and speed up the runtime by 5.7×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document} to 8.5×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document} compared with commercial tool.

Electronics and Optoelectronics Based on Tellurium.

As a true 1Dsystem, group-VIA tellurium (Te) is composed of van der Waals bonded molecular chains within a triangular crystal lattice. This unique crystal structure endows Te with many intriguing properties, including electronic, optoelectronic, thermoelectric, piezoelectric, chirality, and topological properties. In addition, the bandgap of Te exhibits thickness dependence, ranging from 0.31eV in bulk to 1.04eV in the monolayer limit. These diverse properties make Te suitable for a wide range of applications, addressing both established and emerging challenges. This review begins with an elaboration of the crystal structures and fundamental properties of Te, followed by a detailed discussion of its various synthesis methods, which primarily include solution phase, and chemical and physical vapor deposition technologies. These methods form the foundation for designing Te-centered devices. Then the device applications enabled by Te nanostructures are introduced, with an emphasis on electronics, optoelectronics, sensors, and large-scale circuits. Additionally, performance optimization strategies are discussed for Te-based field-effect transistors. Finally, insights into future research directions and the challenges that lie ahead in this field are shared.

Chemical Reaction Simulator on Quantum Computers by First Quantization (II)─Basic Treatment: Implementation.

Chemical simulation is a key application area that can leverage the power of quantum computers. A chemical simulator that implements a grid-based first quantization method has promising characteristics, but an implementation fully in quantum circuits seems to have not been published. Here, we present "crsQ" (chemical reaction simulator Q), which is a quantum circuit generator that generates such a chemical simulator. The generated simulator is capable of antisymmetrization of the initial wave function and time-evolution of the wave function based on the Suzuki-Trotter decomposition. The potential energy term of the Hamiltonian is implemented using arithmetic gates, such as adders, subtractors, multipliers, dividers, and square roots. Circuit diagrams and output samples are shown. The number of qubits in the circuits scales on the order of O(η log η), where η is the number of electrons. Each component of the generated circuit was verified in unit tests. Along with this development, we designed frameworks to ease the development of large-scale circuits, namely, a temporary qubit allocation framework and an abstract syntax tree framework for arithmetic formulas. These frameworks are expected to be useful in large-scale quantum circuit generators.

Symbolic-functional representation inference for gate-level power estimation

We propose SyfriPow, a method for estimating the vectorless average power consumption of gate-level circuits using sparse symbolic matrix inference. SyfriPow employs a probability-based approach, utilizing signal and transition probability to assess power consumption across various nodes. We present a symbolic representation probabilistic model for reasoning signal and transition probability through polynomial-based symbolic inference, incorporating a polynomial approximation strategy for spatial correlations and functional mapping for quick secondary computation. The model is sparsified with GPU accelerated polynomial sparse arithmetic engine, achieving sparse symbolic inference and sparse functional mapping which are implemented on Pytorch. Experiments demonstrate that SyfriPow achieves node-level probabilistic accuracy and significantly improves power accuracy compared to industrial software and academic algorithms, with an average power error of less than 4%. SFM efficiently analyzes large-scale circuits, processing up to 250k nodes in 100 s. SyfriPow can also function as an independent logic prediction engine, surpassing state-of-the-art algorithms in accuracy and speed.

A fixed phase tunable directional coupler based on coupling tuning

The field of photonic integrated circuits has witnessed significant progress in recent years, with a growing demand for devices that offer high-performance reconfigurability. Due to the inability of conventional tunable directional couplers (TDCs) to maintain a fixed phase while tuning the reflectivity, Mach-Zehnder interferometers (MZIs) are employed as the primary building blocks for reflectivity tuning in constructing large-scale circuits. However, MZIs are prone to fabrication errors due to the need for perfect balanced directional couplers to achieve 0-1 reflectivity, which hinders their scalability. In this study, we introduce a design of a TDC based on coupling constant tuning in the thin film Lithium Niobate platform and present an optimized design. Our optimized TDC design enables arbitrary reflectivity tuning while ensuring a consistent phase across a wide range of operating wavelengths. Furthermore, it exhibits fewer bending sections than MZIs and is inherently resilient to fabrication errors in waveguide geometry and coupling length compared to both MZIs and conventional TDCs. Our work contributes to developing high-performance photonic integrated circuits with implications for various fields, including optical communication systems and quantum information processing.

Structural designs and synthesis of co-polycarbonates with cyclohexyl and fluorene structures: Low-dielectric constant, high solubility, and superior mechanical properties

The rapid developments of high-speed communication and large-scale integrated circuits have accelerated the research for insulating dielectric materials with low dielectric constant, low dielectric loss, and good mechanical properties. In this study, a series of polycarbonate resins containing cyclohexyl and fluorene structures are synthesized by melt transesterification, which is low dielectric, highly thermally resistant, and soluble. The effects of fluorene structure contents on the properties of a co-polycarbonate resin were studied systematically. The results showed that the non-polar fluorene group could reduce the molecular polarization of co-polycarbonate, resulting in low permittivity of co-polycarbonate are 2.41–2.71@1 MHz. In addition, the resin has excellent solubility and can be dissolved in NMP, CH2Cl2, THF, and other solvents at room temperature. Furthermore, the co-polycarbonate resins also exhibit superior heat resistance with glass transition temperature (Tg) of 160.6–173.1 °C as well as admirable mechanical properties with a tensile strength of 50.54–70.72 MPa. This makes it a promising candidate for high-speed communications and large-scale integrated circuits.

Multi-objective simulated annealing-based quantum circuit cutting for distributed quantum computation

In the current noisy intermediate-scale quantum (NISQ) era, the number of qubits and the depth of quantum circuits in a quantum computer are limited because of complex operation among increasing number of qubits, low-fidelity quantum gates under noise, and short coherence time of physical qubits. However, with distributed quantum computation (DQC) in which multiple small-scale quantum computers cooperate, large-scale quantum circuits can be implemented. In DQC, it is a key step to decompose large-scale quantum circuits into several small-scale subcircuits equivalently. In this paper, we propose a quantum circuit cutting scheme for the circuits consisting of only single-qubit gates and two-qubit gates. In the scheme, the number of non-local gates and the rounds of subcircuits operation are minimized by using the multi-objective simulated annealing (MOSA) algorithm to cluster the gates and to choose the cutting positions whilst using non-local gates. A reconstruction process is also proposed to calculate the probability distribution of output states of the original circuit. As an example, the 7-qubit circuit of Shor algorithm factoring 15 is used to verify the algorithm. Five cutting schemes are recommended, which can be selected according to practical requirements. Compared with the results of the mixing integer programming (MIP) algorithm, the number of execution rounds is efficiently reduced by slightly increasing the number of nonlocal gates.

A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits

Topological quantum error correction (TQEC) using the surface code is among the most promising techniques for fault-tolerant quantum circuits. The required resource of a TQEC circuit can be modeled as a space-time volume of a three-dimensional diagram by describing the defect movement along the time axis. For large-scale complex problems, it is crucial to minimize the space-time volume for a quantum algorithm with a reasonable physical qubit number and computation time. Previous work proposed an automated tool for bridge compression on a large-scale TQEC circuit. However, the existing automated bridge compression is only for dual defects and not for primal defects. This paper presents an algorithm to simultaneously perform bridge compression on primal and dual defects. In addition, the automatic compression algorithm performs initialization/measurement simplification and flipping to improve the compression. Compared with the state-of-the-art work, experimental results show that our proposed algorithm can averagely reduce space-time volumes by 53%.

Large-Scale Mechanistic Models of Brain Circuits with Biophysically and Morphologically Detailed Neurons.

Understanding the brain requires studying its multiscale interactions from molecules to networks. The increasing availability of large-scale datasets detailing brain circuit composition, connectivity, and activity is transforming neuroscience. However, integrating and interpreting this data remains challenging. Concurrently, advances in supercomputing and sophisticated modeling tools now enable the development of highly detailed, large-scale biophysical circuit models. These mechanistic multiscale models offer a method to systematically integrate experimental data, facilitating investigations into brain structure, function, and disease. This review, based on a Society for Neuroscience 2024 MiniSymposium, aims to disseminate recent advances in large-scale mechanistic modeling to the broader community. It highlights (1) examples of current models for various brain regions developed through experimental data integration; (2) their predictive capabilities regarding cellular and circuit mechanisms underlying experimental recordings (e.g., membrane voltage, spikes, local-field potential, electroencephalography/magnetoencephalography) and brain function; and (3) their use in simulating biomarkers for brain diseases like epilepsy, depression, schizophrenia, and Parkinson's, aiding in understanding their biophysical underpinnings and developing novel treatments. The review showcases state-of-the-art models covering hippocampus, somatosensory, visual, motor, auditory cortical, and thalamic circuits across species. These models predict neural activity at multiple scales and provide insights into the biophysical mechanisms underlying sensation, motor behavior, brain signals, neural coding, disease, pharmacological interventions, and neural stimulation. Collaboration with experimental neuroscientists and clinicians is essential for the development and validation of these models, particularly as datasets grow. Hence, this review aims to foster interest in detailed brain circuit models, leading to cross-disciplinary collaborations that accelerate brain research.

Robust Qubit Mapping Algorithm via Double-Source Optimal Routing on Large Quantum Circuits

Qubit mapping is a critical aspect of implementing quantum circuits on real hardware devices. Currently, the existing algorithms for qubit mapping encounter difficulties when dealing with larger circuit sizes involving hundreds of qubits. In this article, we introduce an innovative qubit mapping algorithm, Duostra, tailored to address the challenge of implementing large-scale quantum circuits on real hardware devices with limited connectivity. Duostra operates by efficiently determining optimal paths for double-qubit gates and inserting SWAP gates accordingly to implement the double-qubit operations on real devices. Together with two heuristic scheduling algorithms, Limitedly Exhaustive Search and Shortest-Path Estimation, it yields results of good quality within a reasonable runtime, thereby striving toward achieving quantum advantage. Experimental results showcase our algorithm’s superiority, especially for large circuits beyond the NISQ era. For example, on large circuits with more than 50 qubits, we can reduce the mapping cost on an average 21.75% over the virtual best results among QMAP, t \(|ket\rangle\) , Qiskit, and SABRE. Besides, for mid-size circuits such as the SABRE-large benchmark, we improve the mapping costs by 4.5%, 5.2%, 16.3%, 20.7%, and 25.7%, when compared to QMAP, TOQM, t \(|ket\rangle\) , Qiskit, and SABRE, respectively.

High-performance single-crystalline In2O3 field effect transistor toward three-dimensional large-scale integration circuits

Formation of a single crystalline oxide semiconductor on an insulating film as a channel material capable of three-dimensional (3D) stacking would enable 3D very-large-scale integration circuits. This study presents a technique for forming single-crystalline In2O3 having no grain boundaries in a channel formation region on an insulating film using the (001) plane of c-axis-aligned crystalline indium gallium zinc oxide as a seed. Vertical field-effect transistors using the single-crystalline In2O3 had an off-state current of 10−21 A μm−1 and electrical characteristics were improved compared with those using non-single-crystalline In2O3: the subthreshold slope was improved from 95.7 to 86.7 mV dec.−1, the threshold voltage showing normally-off characteristics (0.10 V) was obtained, the threshold voltage standard deviation was improved from 0.11 to 0.05 V, the on-state current was improved from 22.5 to 28.8 μA, and a 17-digit on/off ratio was obtained at 27 °C.

Inverse-designed taper configuration for the enhancement of integrated 1 × 4 silicon photonic power splitters.

Once light is coupled to a photonic chip, its efficient distribution in terms of power splitting throughout silicon photonic circuits is very crucial. We present two types of 1 × 4 power splitters with different splitting ratios of 1:1:1:1 and 2:1:1:2. Various taper configurations were compared and analyzed to find the suitable configuration for the power splitter, and among them, parabolic tapers were chosen. The design parameters of the power splitter were determined by means of solving inverse design problems via incorporating particle swarm optimization that allows for overcoming the limitation of the intuition-based brute-force approach. The front and rear portions of the power splitters were optimized sequentially to alleviate local minima issues. The proposed power splitters have a compact footprint of 12.32 × 5 μm2 and can be fabricated through a CMOS-compatible fabrication process. Two-stage power splitter trees were measured to enhance reliability in an experiment. As a result, the power splitter with a splitting ratio of 1:1:1:1 exhibited an experimentally measured insertion loss below 0.61 dB and an imbalance below 1.01 dB within the bandwidth of 1,518-1,565 nm. Also, the power splitter with a splitting ratio of 2:1:1:2 showed an insertion loss below 0.52 dB and a targeted imbalance below 1.15 dB within the bandwidth of 1,526-1,570 nm. Such inverse-designed power splitters can be an essential part of many large-scale photonic circuits including optical phased arrays, programmable photonics, and photonic computing chips.