Large RC Time Constants Research Articles

Unified Equivalent Circuit Model and Optimal Design of <inline-formula><tex-math>$V^{2}$</tex-math> </inline-formula> Controlled Buck Converters

$V^{2}$ control has advantages of simple implementation and fast transient response and is widely used in industry for point-of-load applications. This control scheme is elegant when output capacitors with large RC time constant are employed, such as OSCON capacitors. However, in most cases using capacitors with small RC time constant, such as ceramic capacitors, instability problem will occur. Previous modeling methods including sampled-data modeling, discrete-time analysis, time-domain analysis, and describing function are all very mathematical and difficult to apply for practical engineers as little physical insight can be extracted. Up to now, no equivalent circuit model is proposed which is able to predict the instability issue and serve as a useful design tool for $V^{2}$ control. This paper proposes a unified equivalent circuit model which is applicable to all types of capacitors by considering the effect of capacitor voltage ripple. The equivalent circuit provides the physical insight of $V^{2}$ control as a nonideal voltage source, a dual concept of previous nonideal current source for current-mode control. The equivalent circuit model is a simple yet accurate complete model and is very helpful for design purpose. Optimal design guidelines for point-of-load applications are provided. The proposed equivalent circuit model is applicable to both variable frequency modulation and constant frequency modulation. The equivalent circuit model and design guidelines are verified with Simplis simulation and experimental results.

Deconvolution in Potentiometric SECM

AbstractOne of the main limitations of potentiometric scanning electrochemical microscopy (SECM) is the large RC time constant, and therefore long response time of the cell. A relatively long equilibration interval has to be allowed before sampling at each data acquisition point to reach equilibrium potential, and avoid image distortion. In this paper, we present a method to get high‐quality, low distortion images, without increasing scan time. The convolution function causing the distortion can be expressed from the response function of the potentiometric cell. A model system was studied with high scan rate, then the image was deconvoluted using the inverse of the potentiometric response function to calculate the equilibrium potential for each data acquisition point from the respective observed values.

Pseudo-Continuous-Time Readout Circuit for a 300$^\circ$/s Capacitive 2-Axis Micro-Gyroscope

The interface for a capacitive 2-axis micro-gyroscope is implemented in a 0.35-¿m HVCMOS technology with an active area of 2.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Compared to a regular continuous-time interface with large on-chip RC time constants, the reduction of the chip area is made possible by the pseudo-continuous-time readout technique, of which a detailed analysis is presented in this paper. The technique allows a dc biasing voltage to be used for the detection and does not require any large RC time constants to be implemented. For the sensor that was implemented the x- and y axis noise floors are 0.015°/s/¿Hz and 0.041°/s/¿Hz . The supply current and voltage for the chip, including the charge pump and the drive and sense interfaces, are 1.8 mA and 2.5-3.6 V, respectively. The supply current of a single sense readout channel is approximately 0.4 mA.

Si microphotonics for optical interconnection

This paper reviews current status of silicon microphotonics and the recent prototype of on-chip optical interconnection. Si microphotonics pursues complementary metal oxide semiconductor (CMOS)-compatibility of photonic devices to reduce the materials diversity eventually to integrate on Si chips. Fractal optical H-trees have been implemented on a chip and found to be a technology breakthrough beyond metal interconnection. It has shown that large RC time constants associated with metal can be eliminated at least long distant data communication on a chip, and eventually improve yield and power issues. This has become the world's first electronic and photonic integrated circuits (EPICs) and the possibility of at least 10 GHz clocking for personal computers has been demonstrated.

Characterization of GaN Schottky barrier photodetectors with a low-temperature GaN cap layer

By using organometallic vapor phase epitaxy we have prepared i-GaN/low temperature (LT) GaN/Ni/Au (sample A) and i-GaN/Ni/Au (sample B) Schottky barrier ultraviolet (UV) photodiodes (PDs). It was found that we could significantly reduce leakage current and achieve a much larger photocurrent to dark current contrast ratio by introducing a LT GaN on top of the conventional nitride-based UV PDs. With an incident light wavelength of 350 nm and a −1 V reverse bias, it was found that the measured responsivity was around 0.1 and 0.37 A/W for samples A and B, respectively. Furthermore, it was found that the operation speed of sample A is slower than that of sample B due to the highly resistive LT GaN layer induced large RC time constant.

GaN Schottky barrier photodetectors with a low-temperature GaN cap layer

By using organometallic vapor phase epitaxy, we have prepared i-GaN/low-temperature (LT) GaN/Ni/Au (sample A) and i-GaN/Ni/Au (sample B) Schottky barrier UV photodiodes (PDs). It was found that we could significantly reduce the leakage current and achieve a much larger photocurrent to dark current contrast ratio by introducing a LT GaN on top of the conventional nitride-based UV PDs. With incident light wavelength of 350 nm and a −1 V reverse bias, it was found that the measured responsivity was around 0.1 and 0.37 A/W for samples A and B, respectively. Furthermore, it was found that the operation speed of sample A is slower than that of sample B due to the highly resistive LT–GaN layer induced large RC time constant.

Refractory metal silicides for VLSI applications

Results of a recent program undertaken at Bell Laboratories on silicide gate technology are reviewed with particular reference to the TaSi2/n+ poly-Si structure. This high-conductivity refractory gate structure greatly alleviates the layout and routing problems due to large RC time constants of fine-line poly-Si interconnects. This review contains a discussion of the metallurgical effects, associated with sintering metal and metal–silicon alloy films on polycrystalline silicon, oxidation behavior of silicides, their MOS (process) compatibility, the generic reliability, and trade-offs involved in the selection of a silicide from the group TiSi2, TaSi2, MoSi2 and WSi2.