Large Memory Research Articles

Three-Objects-Three-Places Episodic Memory Test to Screen Mild Cognitive Impairment and Mild Dementia: Validation in a Memory Clinic Population.

The Three-Objects-Three-Places (3O3P) test is a 5-minscreen for episodic memory impairment due to Alzheimer's disease, known for its briefness and easy administration, culture- and language-free nature, and the absence of specific equipment. However, no studies have validated its potential in memory clinic cohorts. The aim of this study was to test its convergent, discriminant, and known-group validities and to define thresholds for its clinical use. We included 2062 cognitively unimpaired (CU), mild cognitive impairment (MCI) and dementia patients from the Geneva Memory Center cohort who underwent the 3O3P test in the context of clinical practice. Convergent and discriminant validities were assessed using an exploratory factor analysis. The known-group validity was assessed in CU vs. MCI and dementia using the area under the curve (AUC). 3O3P test scores vs. amyloid and tau positivity, neurodegeneration, and cognition (ATNC) were assessed using the Kruskal-Wallis test. The 3O3P test cut-offs were calculated using sensitivity, specificity, PPV, NPV, and accuracy. Mean age was 72 years (SD = 11), 60% were female, mean education was 13 years (SD = 4), and mean MMSE was 25 (SD = 5). The 3O3P and Delayed Total Recall tests loaded strongly on the "memory" factor and weakly on "non-memory" factors. The 3O3P test can discriminate CU vs. MCI (AUC = 0.71) and dementia (AUC = 0.92). Higher 3O3P scores were associated with lower prevalence of ATNC (p < 0.001). A 3O3P value of 7 can detect MCI and dementia patients. The 3O3P test has demonstrated good convergent, discriminant, and known-group validity in a large memory clinic population.

Large Electromechanical Response and Field-Induced Shape Memory Effect in Ferroelectric Ceramics.

Electric-field-induced shape memory effect has potential applications in electromechanical actuator. Here, this study proposes the a phase structure design routine in (1-x)(75Na0.5Bi0.5TiO3-25SrTiO3)-xPbTiO3 ceramics to obtain large electromechanical response and shape memory effect. It is found that the shape memory effect is closely related to the bending deformation induced by asymmetric polarization between positive and negative electrodes, which is resulted from the reductions of Bi3+ and Pb2+ because of electron injection from negative electrode. In addition, the content of ferroelectric phase with P4mm structure and c/a ratio increase with PbTiO3 content increasing, and the coercive field of the ceramics is also enhanced by the PbTiO3 addition, Combing the crystal structure and chemical composition, the field-induced deformation achieves 2.77% and shape memory effect is 1.75% at 80kVcm-1 and 0.1Hz in the ceramic with the content of PbTiO3 is 40%.

Low interface state density and large capacitive memory window using RF sputtered NiO nanoparticles decorated MgZnO thin film

NiO nanoparticles (NPs) synthesized using glancing angle deposition (GLAD) technique over MgZnO thin film was used to design a novel memory device. The NiO NPs with average diameter ~ 9.5 nm was uniformly distributed over the MgZnO thin film surface. The MgZnO thin film/NiO NPs memory device when measured for the C-V hysteresis characteristics at varying sweep voltage demonstrated a charge trapping and de-trapping mechanism. Moreover, the device exhibited low interface states density (Dit) (1.45 × 1010 eV− 1 cm− 2) at 1 MHz and large capacitive memory of ~ 6 V at ± 7 V. The large memory window was attributed to the better interface quality between MgZnO thin film and NiO NPs. Additionally, the device also exhibited good endurance over 1000 programme/erase cycles and longer time charge retention up to 2 × 104 s. The improved performance of device and more charge accumulation capacity was primarily due to the large effective area and quantum confinement effect owing to NiO NPs. Further, on performing a resistive switching analysis, the device could show a good on-off ratio (RHRS/RLRS) of 1.24 × 102. Therefore, the proposed device structure can be a good option for future memory applications.

A Purely Real-Valued Fast Estimator of Dynamic Harmonics for Application in Embedded Monitoring Devices in Power-Electronic Grids

Dynamic harmonic estimation is important for the monitoring and control of power-electronic grids. But the high-precision dynamic harmonic estimation algorithms usually have a heavy computational burden and occupy a large memory space, making them difficult to implement in the embedded platform. Thus, the motivation of this paper lies in providing an estimator with low computational complexity and less storage space consumption. A purely real-valued fast dynamic harmonics estimator is proposed. Firstly, a purely real-valued estimation model is established based on the Taylor series expansion on the time-varying amplitude and phase angle. Secondly, the estimation filter bank is computed in the least-squares sense, and the corresponding estimation error is theoretically analyzed. Finally, the purely real-valued fast dynamic harmonics estimator is designed. The advantage includes significantly reducing the computational complexity and memory space consumption while maintaining high-precision estimation. The testing results show that the proposed estimator can achieve the highest harmonics estimation precision under dynamic conditions. The frequency error, magnitude error, and phase angle error are less than 5 × 10−2 Hz, 7 × 10−1%, and 8 × 10−2 degrees, respectively, which verifies the advantage of high-precision estimation. The proposed estimator achieves a computational speed-up of approximately 430, 396, and 330 times compared to the Prony method, ESPRIT method, and iterative Taylor Fourier transform method, respectively. The computational load rate for executing the proposed estimator on the embedded prototype using C6748 DSP for estimating 50 harmonics is approximately only 2.05%, which verifies the advantage of a low computational load rate.

Review of: "The nanographene charge-trapping memory exhibits large gate memory (4.5 V) at low operating voltage (8 V)"

Review of: "The nanographene charge-trapping memory exhibits large gate memory (4.5 V) at low operating voltage (8 V)"

Review of: "The nanographene charge-trapping memory exhibits large gate memory"

Review of: "The nanographene charge-trapping memory exhibits large gate memory"

Write Endurance Enhanced and Large Memory Window of GeSe-Based Selector-Only Memory With Indium Doping Scheme

Write Endurance Enhanced and Large Memory Window of GeSe-Based Selector-Only Memory With Indium Doping Scheme

Sheep-YOLO: a lightweight daily behavior identification and counting method for housed sheep

Abstract Daily behavior detection and monitoring of sheep is crucial for assessing their health status. In recent years, computer vision has been widely used in livestock behavior detection, but it usually requires large memory and computational resources. In addition, most studies have focused only on the behavior of sheep during the day, while the behavior of sheep during the night is equally important for a comprehensive understanding of their health status and well-being. Therefore, in this study, we developed a lightweight daily behavior detection and counting method for housed sheep to detect lying, feeding, and standing behaviors, and to count the number of each behavior as well as the total number of sheep. First, we propose a new PCBAM module and incorporate it into the neck part of YOLOv8n to enhance the feature information contained in the feature map, second, we use the slim neck design paradigm incorporating GSConv to lighten and improve the model operation efficiency, and finally, we reconstruct the detection head to eliminate the redundant small target detection head, reduce the model computational burden, and improve the detection performance of medium and large targets. The Sheep-YOLO model is validated using the daily behavioral dataset of housed sheep, and the experimental results show that the improved model is effective in detecting sheep behavior in complex environments, and the mAP@0.5 is improved by 5.4% compared to the baseline model, and in particular, the lying and feeding behaviors of sheep are improved by 7.2% and 8.8%, respectively. Comparative experiments with other mainstream target detection algorithms validate the advantages of our proposed model for sheep behavior detection. This study provides an effective solution for behavioral detection and counting of housed sheep.

A multi-scale path-planning method for large-scale scenes based on a framed scale-elastic grid map

ABSTRACT Environment modeling serves as the foundation for path planning in unmanned systems. Single-scale maps have many nodes and impose large memory requirements; tree-based multi-scale grid maps used for representing large-scale urban scenes have limited aggregation ability in the presence of dimensional anisotropy. This study proposes a novel multi-scale map-construction method based on a scale-elastic discrete grid structure. The method provides more flexible node aggregation in grid-based representations, reducing the number of grid and border-grid nodes while maintaining the same modeling accuracy. Furthermore, a novel multi-scale A* path-planning algorithm that modifies the neighborhood-expansion phase of A* is proposed to reduce the number of algorithm search nodes in framed multi-scale maps while ensuring optimal path planning. The experimental results demonstrate that the proposed map-construction method requires 71.5% fewer grids and 10.8% fewer border grids than framed-octree grid maps in three-dimensional scenarios with the same modeling accuracy. Consequently, memory requirements are smaller, making this method more efficient on devices with limited performance. The multi-scale A* algorithm also improves path-planning efficiency by reducing the number of search nodes. The proposed method is suitable for path planning in large-scale and complex urban scenes.

Sliding ferroelectric memories and synapses based on rhombohedral-stacked bilayer MoS2

Recent advances have uncovered an exotic sliding ferroelectric mechanism, which endows to design atomically thin ferroelectrics from non-ferroelectric parent monolayers. Although notable progress has been witnessed in understanding the fundamental properties, functional devices based on sliding ferroelectrics remain elusive. Here, we demonstrate the rewritable, non-volatile memories at room-temperature with a two-dimensional (2D) sliding ferroelectric semiconductor of rhombohedral-stacked bilayer MoS2. The 2D sliding ferroelectric memories (SFeMs) show superior performances with a large memory window of >8 V, a high conductance ratio of above 106, a long retention time of >10 years, and a programming endurance greater than 104 cycles. Remarkably, flexible SFeMs are achieved with state-of-the-art performances competitive to their rigid counterparts and maintain their performances post bending over 103 cycles. Furthermore, synapse-specific Hebbian forms of plasticity and image recognition with a high accuracy of 97.81% are demonstrated based on flexible SFeMs.

Memory Checking Requires Logarithmic Overhead

We study the complexity of memory checkers with computational security and prove the first general tight lower bound. Memory checkers, first introduced over 30 years ago by Blum, Evans, Gemmel, Kannan, and Naor (FOCS ’91, Algorithmica ’94), allow a user to store and maintain a large memory on a remote and unreliable server by using small trusted local storage. The user can issue instructions to the server and after every instruction, obtain either the correct value or a failure (but not an incorrect answer) with high probability. The main complexity measure of interest is the size of the local storage and the number of queries the memory checker makes upon every logical instruction. The most efficient known construction has query complexity O (log n /log log n ) and local space proportional to a computational security parameter, assuming one-way functions, where n is the logical memory size. Dwork, Naor, Rothblum, and Vaikuntanathan (TCC ’09) showed that for a restricted class of “deterministic and non-adaptive” memory checkers, this construction is optimal, up to constant factors. However, going beyond the small class of deterministic and non-adaptive constructions has remained a major open problem. In this work, we fully resolve the complexity of memory checkers by showing that any construction with local space p and query complexity q must satisfy \[ p \ge \frac{n}{(\log n)^{O(q)}} \;. \] This implies, as a special case, that q ≥ Ω (log n /log log n ) in any scheme, assuming that p ≤ n 1 − ε for ε &gt; 0. The bound applies to any scheme with computational security, completeness 2/3, and inverse polynomial in n soundness (all of which make our lower bound only stronger). We further extend the lower bound to schemes where the read complexity q r and write complexity q w differ. For instance, we show the tight bound that if q r = O (1) and p ≤ n 1 − ε for ε &gt; 0, then q w ≥ n Ω (1) . This is the first lower bound, for any non-trivial class of constructions, showing a read-write query complexity trade-off. Our proof is via a delicate compression argument showing that a “too good to be true” memory checker can be used to compress random bits of information. We draw inspiration from tools recently developed for lower bounds for relaxed locally decodable codes. However, our proof itself significantly departs from these works, necessitated by the differences between settings.

Memory-Non-Linearity Trade-Off in Distance-Based Delay Networks.

The performance of echo state networks (ESNs) in temporal pattern learning tasks depends both on their memory capacity (MC) and their non-linear processing. It has been shown that linear memory capacity is maximized when ESN neurons have linear activation, and that a trade-off between non-linearity and linear memory capacity is required for temporal pattern learning tasks. The more recent distance-based delay networks (DDNs) have shown improved memory capacity over ESNs in several benchmark temporal pattern learning tasks. However, it has not thus far been studied whether this increased memory capacity comes at the cost of reduced non-linear processing. In this paper, we advance the hypothesis that DDNs in fact achieve a better trade-off between linear MC and non-linearity than ESNs, by showing that DDNs can have strong non-linearity with large memory spans. We tested this hypothesis using the NARMA-30 task and the bitwise delayed XOR task, two commonly used reservoir benchmark tasks that require a high degree of both non-linearity and memory.

A Coplanar Crystalline InGaO Thin Film Transistor with SiO2 Gate Insulator on ZrO2 Ferroelectric Layer: A New Ferroelectric TFT Structure

AbstractFerroelectric transistors with a large memory window (MW) and operational stability have been of increasing interest recently. In this study, a ferroelectric thin‐film transistor (FE‐TFT) with a novel metal‐insulator‐semiconductor‐ferroelectric (MISF) structure is proposed. With the ferroelectric layer located under the semiconductor, the TFT process can be similar to a conventional coplanar structure with a SiO2 gate insulator (GI). In this work, both FE and active semiconductors are deposited by spray pyrolysis which is beneficial for large‐area and low‐cost manufacturing. The FE ZrO2 by spray pyrolysis has a nanocrystalline phase, and the semiconductor InGaO shows a polycrystalline structure. The TFT exhibits a MW of 5.6 V with an operating voltage range of −10–10 V. The device shows a low leakage current of 10−12 A, and thus the on/off ratio is &gt;107 at VDS = 1.0 V. The device shows stable performance with increasing temperatures up to 80 °C. The endurance of the device is 5000 cycles at 0.1 Hz pulse with a negligible variation of MW less than 0.1 V, indicating excellent operational stability.

A Large Window Nonvolatile Transistor Memory for High-Density and Low-Power Vertical NAND Storage Enabled by Ferroelectric Charge Pumping

A Large Window Nonvolatile Transistor Memory for High-Density and Low-Power Vertical NAND Storage Enabled by Ferroelectric Charge Pumping

Professional Web Application for Lidar Data Visualization and Metric Inspection

Abstract Lidar data is difficult to access for regular users due to the very large memory volume required and the need to handle it with powerful computers and quite expensive specialized software. The presented web application is offered for free in the LidarTools version and at a low cost in the LidarMap version, which combines shape-type vector data with the Lidar point cloud. The application uses a POTREE structure adapted for rapid visualization functions but enhanced with functions for measuring in the point cloud (distances, areas), visualization functions, profile extraction, statistical functions, semi-automatic vectorization functions of linear objects (power lines), coordinate transformation functions, as well as other functions specific to users of such data. It is also presented here the project for stereo vectoring module in LidarMap application.

Disturb and its Mitigation in Ferroelectric Field-Effect Transistors With Large Memory Window for NAND Flash Applications

Disturb and its Mitigation in Ferroelectric Field-Effect Transistors With Large Memory Window for NAND Flash Applications

Cognitive and physical activity are related to increased cognitive reserve in a large memory clinic cohort

Cognitive and physical activity are related to increased cognitive reserve in a large memory clinic cohort

F3: Fast and Flexible Network Telemetry with an FPGA coprocessor

Traffic monitoring in the dataplane is vital for reacting to network events such as microbursts, incast, and attacks. However, current solutions are constrained by the limited resources available on modern ASICs and don't provide the flexibility required to identify repeating patterns, such as applications whose flows communicate with a server at regular intervals. While such flexibility can be achieved using a co-processing CPU, it is generally too slow to provide insights quickly enough. In this paper, we show how an FPGA co-processor placed alongside the switching pipeline enables flexible traffic monitoring at data plane rates. While FPGAs have large memory and expressive processing, their throughput is significantly lower than switch ASICs. To bridge the throughput gap, we split query execution between the switch and FPGA and present methods that prevent processing all packets in FPGA. As a result, our system misses up to 5.0x fewer DDoS attack vectors than ACC-Turbo, the state-of-the-art on-switch solution, and up to 24% fewer microburst-contributing flows for the same precision rate.

EdgeCross: Cloud Scale Traffic Management at Peering Edges

Cloud providers deployed dozens of PoPs and data centers globally to serve billions of geo-distributed users. The traffic management at peering edges has become a key capability of cloud network operators to meet the diverse demands of users. With the rapid growth of cloud applications, users have recently announced new performance requirements, e.g., achieving latency as low as possible instead of maintaining a specified delay. The conventional inter-domain bandwidth allocation approach, which aims to reduce the high operating expenditures of bandwidth usage, fails to meet these new requirements. We further reveal that the flow scheduling among PoPs may fail due to the limited link capacity hidden by the cloud private backbone network controller. Therefore we seek a new traffic management at peering edges. We propose a new controller framework, EdgeCross, that satisfies not only users' emerging demands but maintains low operating costs. The large number of fine-grain application-aware flows and the consideration of backbone links' capacity lead to very high complexity of routing computation and verification for the controller. EdgeCross introduces a two-phase operation that first achieves the low-expense bandwidth allocation according to the standard 95th percentile billing model and then allocates specified flows to peering edges based on users' requirements. EdgeCross further reduces large memory consumption by proposing an effective routing table compression approach. The evaluation based on a production network with 16 PoPs has shown that EdgeCross can successfully process the routes of 1 billion flows in 10 seconds, reduce the average delay for performance-sensitive flows by 2 milliseconds compared to traditional BGP, and is able to save the bandwidth cost by 10-26% compared to the state-of-the-art Cascara.

Modified Born series with virtual absorbing boundary enabling large-scale electromagnetic simulation

Numerical electromagnetic field solvers are significant for nanophotonic and photoelectronic technology, especially for computational imaging, metasurface, and biomedical microscopy, in which large-scale simulations serve as the core. Conventionally, these simulations use absorbing boundary conditions (ABC) to simulate open-domain systems. However, the existing ABCs require large memory to sufficiently suppress reflection at boundaries, which is prohibitive for large-scale applications. This work proposes a virtual absorbing boundary condition based on the angular spectrum method (ASM) to reduce the memory usage of ABC. The ASM is used to cover the polluted field in the boundary region, which eliminates the need to store the field in the boundary region. Combined with the Fourier transforms-based modified Born series, memory usage can be reduced to a level close to the theoretical limit. This proposed method offers a substantial boost for applications related to large-scale simulations and memory-constrained devices like GPU.