Large Gate Research Articles

Bending strain induced photocurrent crossover from positive to negative in the flexible organic phototransistors

The understanding of bending strain effects on the performances of flexible organic phototransistors (FOPTs) is of great importance. In this manuscript, two kinds of FOPTs-single layer of copper phthalocyanine (CuPc) (SL-FOPTs) and hybrid planar bulk-heterojunction of CuPc/CuPc:PTCDA (HPBHJ-OPTs) with PTCDA denotes 3,4,9,10-perylenete-acarboxylic dianhydride, with polyvinyl alcohol as the gate dielectric but different active layer, were fabricated and their strain dependent performances investigated, respectively. For SL-FOPTs, at a given light intensity, with the bending-strain increasing, the photocurrent increases at first, and then decreases after reaching a maximum. A crossover from positive to negative occurs in this process, and the critical strain at which the crossover occurs increases with the illumination light intensity. Different from the observation in SL-FOPTs, the Idark ~ strain curves in HPBHJ-FOPTs exhibit obtuse small peaks at low gate voltages of |Vg|≦10 V, and minimums at large gate voltages of |Vg|≧ 20 V. At large gate voltages with increasing bending strain, the photocurrent of HPBHJ-OPTs decreases and become negative (from positive) at first, with the decreasing rate nearly proportional to the gate voltage, and then increase after reaching a negative minimum. The physical origin of observed photocurrent crossover from positive to negative with increasing bending strain is discussed.

Techniques for fault-tolerant decomposition of a multicontrolled Toffoli gate

Physical implementation of scalable quantum architectures faces an immense challenge in the form of fragile quantum states. To overcome it, quantum architectures with fault tolerance are desirable. These are achieved currently by using a surface code along with a transversal gate set. This indicates the need for decomposition of universal $n$-qubit multicontrolled Toffoli ($n$-MCT) gates using a transversal gate set. Additionally, the transversal non-Clifford phase gate incurs high latency, which makes it an important factor to consider during decomposition. Additionally, the decomposition of a large MCT gate without ancillas presents an additional hurdle. In this paper, we address both of these issues by introducing the $\mathrm{Clifford}+{Z}_{N}$ gate library. We present an ancilla-free decomposition of MCT gates with linear phase depth and quadratic phase count. Furthermore, we provide a technique for decomposition of MCT gates in unit phase depth using the $\mathrm{Clifford}+{Z}_{N}$ library, albeit at the cost of ancillary lines and exponential phase count.

Breakdown voltage enhancement in GaN channel and AlGaN channel HEMTs using large gate metal height**Project supported by the National Key Science & Technology Special Project of China (Grant No. 2017ZX01001301), the National Key Research and Development Program of China (Grant No. 2016YFB0400100), and the National Natural Science Foundation of China (Grant Nos. 51777168 and 61801374).

A large gate metal height technique is proposed to enhance breakdown voltage in GaN channel and AlGaN channel high-electron-mobility-transistors (HEMTs). For GaN channel HEMTs with gate–drain spacing LGD = 2.5 μm, the breakdown voltage VBR increases from 518 V to 582 V by increasing gate metal height h from 0.2 μm to 0.4 μm. For GaN channel HEMTs with LGD = 7 μm, VBR increases from 953 V to 1310 V by increasing h from 0.8 μm to 1.6 μm. The breakdown voltage enhancement results from the increase of the gate sidewall capacitance and depletion region extension. For Al0.4Ga0.6N channel HEMT with LGD = 7 μm, VBR increases from 1535 V to 1763 V by increasing h from 0.8 μm to 1.6 μm, resulting in a high average breakdown electric field of 2.51 MV/cm. Simulation and analysis indicate that the high gate metal height is an effective method to enhance breakdown voltage in GaN-based HEMTs, and this method can be utilized in all the lateral semiconductor devices.

Large Current Driven Domain Wall Mobility and Gate Tuning of Coercivity in Ferrimagnetic Mn4N Thin Films.

Spintronics, which is the basis of a low-power, beyond-CMOS technology for computational and memory devices, remains up to now entirely based on critical materials such as Co, heavy metals and rare-earths. Here, we show that Mn4N, a rare-earth free ferrimagnet made of abundant elements, is an exciting candidate for the development of sustainable spintronics devices. Mn4N thin films grown epitaxially on SrTiO3 substrates possess remarkable properties, such as a perpendicular magnetization, a very high extraordinary Hall angle (2%) and smooth domain walls at the millimeter scale. Moreover, domain walls can be moved at record speeds by spin-polarized currents, in absence of spin-orbit torques. This can be explained by the large efficiency of the adiabatic spin transfer torque, due to the conjunction of a reduced magnetization and a large spin polarization. Finally, we show that the application of gate voltages through the SrTiO3 substrates allows modulating the Mn4N coercive field with a large efficiency.

Deterministic direct growth of WS2 on CVD graphene arrays

The combination of the exciting properties of graphene with those of monolayer tungsten disulfide (WS2) makes this heterostack of great interest for electronic, optoelectronic and spintronic applications. The scalable synthesis of graphene/WS2 heterostructures on technologically attractive substrates like SiO2 would greatly facilitate the implementation of novel two-dimensional (2D) devices. In this work, we report the direct growth of monolayer WS2 via chemical vapor deposition (CVD) on single-crystal graphene arrays on SiO2. Remarkably, spectroscopic and microscopic characterization reveals that WS2 grows only on top of the graphene crystals so that the vertical heterostack is selectively obtained in a bottom-up fashion. Spectroscopic characterization indicates that, after WS2 synthesis, graphene undergoes compressive strain and hole doping. Tailored experiments show that such hole doping is caused by the modification of the SiO2 stoichiometry at the graphene/SiO2 interface during the WS2 growth. Electrical transport measurements reveal that the heterostructure behaves like an electron-blocking layer at large positive gate voltage, which makes it a suitable candidate for the development of unipolar optoelectronic components.

Improving the transconductance flatness of InAlN/GaN HEMT by modulating VT along the gate width

A modulated VT HEMT with improved gm flatness is demonstrated for high linearity application. The modulated VT HEMT was achieved by connecting two elements with different VT values in parallel along the gate width, realizing a flat resulting transfer curve, and the two different VT elements were fabricated by recessing part area of the barrier along the gate width under the gate region. The proposed HEMT shows a gate voltage swing as high as 5.4 V, a high drain current of approximately 2 A mm−1, and an fT/fmax of 63/125 GHz with a much flatter profile within the large gate voltage range.

Application of an embedded general-purpose computing platform to passive acoustic monitoring

JASCO Applied Sciences has developed a novel passive acoustic monitoring system, the OceanObserverTM, that has been fielded in undersea and surface AUVs as well as on buoys and sub-sea observatories. The hardware is based on the Zynq system-on-a-chip (SoC), which features a large field-programmable gate array (FPGA) and two ARM processing cores. The FPGA is used to implement real-time filtering for the analog-to-digital converters and a real-time detector for odontocete clicks. JASCO’s PAMlab JAVA software has been adapted to run in the ARM processors. This allows for the detector algorithms to be tested and proven using recorded data sets, and the deployment of algorithms in the real-time hardware using the same proven software baseline. The advantages of this approach for rapidly adapting generic hardware to diverse monitoring projects will be highlighted.

Gate Drive Technology Evaluation and Development to Maximize Switching Speed of SiC Discrete Devices and Power Modules in Hard Switching Applications

To understand the limitation of maximizing the switching speed of SiC low-current discrete devices and high-current power modules in hard switching applications, double pulse tests are conducted and the testing results are analyzed. For power modules, the switching speed is generally limited by the parasitics rather than the gate drive capability. For discrete SiC devices, the conventional voltage source gate drive (VSG) is not sufficient to maximize the switching speed even if the external gate resistance is minimized. The limitation of existing current source gate drives (CSG) is analyzed, and a CSG dedicated for SiC discrete devices is proposed, which can provide constant current during the switching transient, regardless of the high Miller voltage and large internal gate resistance. Compared with the conventional VSG, the proposed CSG achieves 67% faster turn on time and 50% faster turn off time, and 68% reduction in switching loss at full-load condition.

Investigation of Dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Under Switching Operation in Schottky-Type p-GaN Gate HEMTs

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs.

Two-Dimensional WSe2/Organic Acceptor Hybrid Nonvolatile Memory Devices Based on Interface Charge Trapping.

Two-dimensional (2D) materials, with atomic thickness and unique electronic structure, hold great potentials in electronic device applications. Charge transfer at the interface of 2D materials further provides a versatile platform for applications in electronics. Here, we report nonvolatile memory devices based on interface charge trapping between 2D WSe2 and organic electron acceptors. The 2D WSe2-organic acceptor hybrid structure exhibits a high storage performance, such as large gate memory windows, high on/off ratios (>103), and long retention time (>1000 s). Further analysis revealed that organic acceptors with a stronger electron affinity (i.e., higher redox potential) have a larger electron-trapping ability and hence a better memory performance.

Frequency- and Temperature-Dependent Gate Reliability of Schottky-Type ${p}$ -GaN Gate HEMTs

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage ( I–V ) characteristics and threshold voltage ( ${V}_{\text {TH}}$ ) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier.

An SVD Processor Based on Golub–Reinsch Algorithm for MIMO Precoding With Adjustable Precision

A singular-value-decomposition (SVD) processor having adjustable precision for $8 \times 8$ multiple-input multiple-output precoding systems supporting up to 256-quadrature amplitude modulation (QAM) is designed and implemented. The memory-based architecture that consists of eight processing elements, each having two coordinate rotation digital computer modules, is employed. Golub–Reinsch SVD (GR-SVD) algorithm with Rayleigh quotient shift is used. Thus, two-phase operations are performed including bidiagonalization and implicit shifted QR for diagonalization. The split, deflation, and shift techniques of GR-SVD are helpful to accelerate the diagonalization and reduce the computation complexity. To cover the precision requirements for compact 256-QAM constellation and spatially correlated channels, hybrid datapath representations are used. The threshold for split and deflation can be adjusted and thus the precision of the SVD processor is variable according to the requirements. Although the high precision results in a large gate count, this SVD processor in 40-nm CMOS technology can complete the decomposition of an $8 \times 8$ matrix in 313 clock cycles averagely and is able to provide a throughput rate of 591K matrix/s with good power efficiency.

Effects of High Temperatures on Cell Reading, Programming, and Erasing of Schottky Barrier Charge-Trapping Memories

This paper examines the temperature effect of Schottky barrier source/drain charge-trapping memories. The current–voltage curves and programming/erasing characteristics are experimentally investigated at room temperature and higher 85 °C and 125 °C. 2-D device simulations were performed to elucidate the physical mechanisms of Schottky barrier cell devices at high temperatures. For Schottky barrier charge-trapping cells, two different mechanisms of ambipolar conduction are classified: 1) thermionic emission and 2) Schottky barrier tunneling. The thermionic emission is susceptible to variations of high temperatures, leading to considerable shifts in logarithmic scale off-state drain-currents at low gate voltages. However, at adequately large gate voltages, the Schottky barrier tunneling plays a key role in contributing drain currents. The Schottky barriers and associated tunneling are relatively insensitive to the variations of device temperatures, preserving favorable temperature-insensitive programming and erasing Schottky barrier charge-trapping cells for use in the high-temperature automotive industry.

Lateral GaN Jfet Devices on Large Area Engineered Substrates for Robust Power Switching

GaN-based power switching devices are of significant interest for high efficiency power conversion circuits in medium voltage applications. However, there are still significant challenges preventing mass production and widespread adoption. In particular, lateral HEMT devices lack avalanche capability for rugged power switching, vertical device technology is not mature, the manufacturing cost associated with small diameter substrates is relatively high, and CTE mismatch issues create limitations on epi thickness as well as bow issues for GaN-on-Si. As a scalable substrate solution, Qromis, Inc. has developed commercial substrates designated QST™ which are engineered to be thermally matched to GaN, enabling thick epitaxial layers capable of >1kV devices on 200 mm diameter wafers suitable for fabrication in a CMOS fabrication facility. Taking advantage of this platform, we present a GaN-based lateral junction gate field effect transistor (JFET) device structure for robust power switching. The p-GaN gate functions to collect secondary holes while a second buried p-GaN blocking layer is implemented to pull the electric field below the surface as in a Reduced Surface Field (RESURF) structure. Unlike a HEMT process, the LJFET epi design and process sequence requires appropriate design of the doping in the buffer, gate, and channel layers for charge balancing, and additional process modules for N+ doping for source/drain contact (via ion implantation), low-damage p+ etching to define the gate, and N implantation to partially compensate the p- layer for field management. These steps have been independently optimized. Device testing indicated high current capability (>1A) in large gate width devices and high current density (~200 mA/mm) in smaller devices. The discrepancy is attributed to a processing issue creating spreading resistance in the ohmic contacts indicating a need for thick metallization. Gate continuity was tested by electroluminescence from the forward biased p-n junction, and breakdown tests indicated >1kV blocking capability with low leakage current. In summary, a conceptual prototype for a lateral GaN JFET device was demonstrated experimentally with promising current density and breakdown performance.

Gate‐Tunable Graphene–WSe2 Heterojunctions at the Schottky–Mott Limit

Metal-semiconductor interfaces, known as Schottky junctions, have long been hindered by defects and impurities. Such imperfections dominate the electrical characteristics of the junction by pinning the metal Fermi energy. Here, a graphene-WSe2 p-type Schottky junction, which exhibits a lack of Fermi level pinning, is studied. The Schottky junction displays near-ideal diode characteristics with large gate tunability and small leakage currents. Using a gate electrostatically coupled to the WSe2 channel to tune the Schottky barrier height, the Schottky-Mott limit is probed in a single device. As a special manifestation of the tunable Schottky barrier, a diode with a dynamically controlled ideality factor is demonstrated.

Improving characterization capabilities in new single-photon avalanche diode research.

Many novel and promising single-photon avalanche diodes (SPADs) emerged in recent years. However, some of them may demonstrate a very high dark count rate, even tens of megahertz, especially during the development phase or at room temperature, posing new challenges to device characterization. Gating operation with a width of 10 ns can be used to suppress the dark counts not coincident with the photon arriving time. However, as a side effect of the fast-gating operation, the gating response could be much higher than the avalanche signal and is usually removed by various circuit-based cancellation techniques. Here, we present an alternative method. A high-speed digital storage oscilloscope (DSO) is used to extract the weak avalanche signals from the large gating response background by waveform subtraction in software. Consequently, no complex circuit and precise tuning for each SPAD are needed. The avalanche detection threshold can be reduced to 5% of the full vertical scale of the DSO or 5 mV, whichever is greater. The timing resolution can be better than 2 ps for typical avalanche signals. Optical alignment and calibration are easy. The feasibility of on-wafer test with an RF probe station is discussed. All the advantages and features listed above make this method very useful in new SPAD research.

Current Aperture Vertical <inline-formula> <tex-math notation="LaTeX">$\beta$ </tex-math> </inline-formula>-Ga2O3 MOSFETs Fabricated by N- and Si-Ion Implantation Doping

Depletion-mode vertical Ga2O3 metal-oxide-semiconductor field-effect transistors featuring a current aperture were developed on a halide vapor phase epitaxial drift layer grown on a bulk $\beta $ -Ga2O3 (001) substrate. Three ion implantation steps were employed to fabricate the ${n}^{++}$ source regions, lateral ${n}$ channel, and ${p}$ current blocking layers, where Si and N were selected as the donor and deep acceptor dopant species, respectively. The transistors delivered a drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 $\text{m}\Omega \cdot \text {cm}^{2}$ , and an output current on/off ratio of over 108. High-voltage performance of the present devices was hampered by a large gate oxide field in the off-state causing high gate leakage, a limitation that can be readily overcome through optimized doping schemes and an improved gate dielectric. The demonstration of a planar-gate vertical Ga2O3 transistor based on a highly manufacturable all-ion-implanted process greatly enhances the prospects for Ga2O3-based power electronics.

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (WNW) down to 10 nm as a function of the large back gate bias variation (from +20 to −20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (WNW = 10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (WNW = 220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and −20 V for pMOS), the SS degrades from 61 mV dec−1 (WNW = 10 nm) to 68 mV dec−1 (WNW = 220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (−20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec−1 at the same WNW range, which is a very acceptable results. Additionally, the drain current (ION) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones.

Imaging of Carbon Nanotube Electronic States Polarized by the Field of an Excited Quantum Dot.

Efficient heat dissipation and large gate capacitance have made carbon nanotube field-effect transistors (CNT FETs) devices of interest for over 20 years. The mechanism of CNT FETs involves localization of the electronic structure due to a transverse electric field, yet little is known about the localization effect, nor has the electronic polarization been visualized directly. Here, we co-deposit PbS quantum dots (QDs) with CNTs and optically excite the QD so its excited-state dipolar field biases the local environment of a CNT. Using single-molecule absorption scanning tunneling microscopy, we show that the electronic states of the CNT become transversely localized. By nudging QDs to different distances from the CNT, the magnitude of the localization can be controlled. Different bias voltages probe the degree of localization in different CNT excited states. A simple tight-binding model for the CNT in an electrostatic field provides a semiquantitative model for the observed behavior.

Monolithic GaN Half-Bridge Stages With Integrated Gate Drivers for High Temperature DC-DC Buck Converters

This paper presents a GaN based synchronous buck DC-DC converter, which monolithically integrates gate drivers and a half-bridge power stage in a 3-μm enhancement-mode (E-mode) GaN-on-Si process. The fabricated synchronous converter with integrated gate drivers is based on E-mode GaN MIS-HFETs (metal-insulator-semiconductor heterojunction-field-effect-transistors), which have a large gate swing of 10 V due to the insertion of 20 nm high-k gate insulator Al 2 O 3 . At 100 kHz, the proposed DC-DC integrated circuits (ICs) exhibit good thermal stability at high temperatures up to 250 °C for 25 V down conversion. Furthermore, four different designs (asynchronous and synchronous) including converters with external drivers were systematically evaluated at different input voltages and duty cycles, the GaN-based DC-DC converters with integrated gate drivers exhibit small voltage overshoots and oscillations due to reduced parasitic inductance and chip size. These results validate the advantages of monolithic, lateral integration of half-bridge GaN ICs with gate drivers for high temperature power converters.