Large Field Programmable Gate Array Research Articles

The Octopus processor for the CMS L1 muon trigger for High Luminosity LHC

The upgraded L1 muon trigger system of the CMS experiment in the High Luminosity Large Hadron Collider is based on custom processors featuring large Field Programmable Gate Arrays (FPGAs) connected by large numbers of optical links. These provide the I/O bandwidth and power necessary to process the complex algorithms used during the collection of physics data. The design and performance requirements of these processors creates significant challenges in signal integrity, power delivery, and thermal management. In this paper we describe the Octopus processor, featuring a large Xilinx Virtex Ultrascale+ FPGA and up to 128 links interfaced to optics through high quality twin-ax copper cables. Results on signal integrity at 25 Gb/s and the first demonstration of 50+ Gb/s links with pluggable optics in CMS are also shown, demonstrating bit error rates below 10−15 at a 95% confidence level. The thermal performance is measured inside an Advanced-TCA crate with acceptable thermal margins up to 200 W of chip power. Future improvements are mentioned, potentially allowing operation at up to 300 W.

RETRACTED: Human tracking of track and field athletes based on FPGA and computer vision

An essential issue that sports science faces in understanding the game's flow is to analyze the game's situation. The use of information technology can help to achieve this goal. Computing speed, the size of the system, consider the accuracy of the complex data analysis. From the practical application of views, technical problems can be divided into three significant respects. This article aims to accelerate image recognition and object tracking; propose a one-dimensional data pipeline architecture on a Field-Programmable Gate Array (FPGA). It is met by a small circuit considering calculation and the spatiotemporal data dependency between two high-velocity flows. The volleyball game has been selected as the target application. FPGA design, pre-processing, color filtering, digitization, noise reduction, including such as template matching. Design and implementation by training stations of the Spartan-6 FPGA Xilinx Atlys of the Spartan-6 FPGA LX45 'were evaluated. Computing power will reach per 100 frames at a resolution of SVGA 800 × 600 pixels. Design, excellent with the scalability, can more easily improve the performance in the case of using a large FPGA. The proposed system consists of the Atlys substrate and Atlys VmodCAM stereo camera board. The average accuracy rate before the game situation and the game with 87.1 percent and 65.7 percent. Since the streaming input data, you can improve the precision by taking into account the previous and the next frame. And 90.4 percent will be able to improve to 72.2 percent by using a moving average filter and template matching.

Application of an embedded general-purpose computing platform to passive acoustic monitoring

JASCO Applied Sciences has developed a novel passive acoustic monitoring system, the OceanObserverTM, that has been fielded in undersea and surface AUVs as well as on buoys and sub-sea observatories. The hardware is based on the Zynq system-on-a-chip (SoC), which features a large field-programmable gate array (FPGA) and two ARM processing cores. The FPGA is used to implement real-time filtering for the analog-to-digital converters and a real-time detector for odontocete clicks. JASCO’s PAMlab JAVA software has been adapted to run in the ARM processors. This allows for the detector algorithms to be tested and proven using recorded data sets, and the deployment of algorithms in the real-time hardware using the same proven software baseline. The advantages of this approach for rapidly adapting generic hardware to diverse monitoring projects will be highlighted.

Galapagos: A Full Stack Approach to FPGA Integration in the Cloud

Field-programmable gate arrays (FPGAs) have shown to be quite beneficial in the cloud due to their energy-efficient application-specific acceleration. These accelerators have always been difficult to use and at cloud scale, the difficulty of managing these devices scales accordingly. We approach the challenge of managing large FPGA accelerator clusters in the cloud using abstraction layers and a new hardware stack that we call Galapagos. The hardware stack abstracts low-level details while providing flexibility in the amount of low-level access users require to reach their performance needs.

Development of ROACH Firmware for Microwave Multiplexed X-Ray TES Microcalorimeters

We are developing room temperature electronics based upon the ROACH platform to readout microwave multiplexed X-ray TES. ROACH is an open-source hardware and software platform featuring a large Xilinx Field Programmable Gate Array (FPGA), Power PC processor, several 10 GB Ethernet SFP+ interfaces, and a collection of daughter boards for analog signal generation and acquisition. The combination of a ROACH board, ADC/DAC conversion daughter boards, and hardware for RF mixing allows for the generation and capture of multiple RF tones for reading out microwave multiplexed X-ray TES microcalorimeters. The FPGA is used to generate multiple tones in base band, from 10 MHz to 250 MHz, which are subsequently mixed to RF in the multiple GHz range and sent through the microwave multiplexer. The tones are generated in the FPGA by storing a large lookup table in Quad Data Rate SRAM modules and playing out the waveform to a DAC board. Once the signal has been modulated to RF, passed through the microwave multiplexer, and has been modulated back to base band, the signal is digitized by an ADC board. The tones are modulated to 0 Hz by using a FPGA circuit consisting of a polyphase filter bank, several Xilinx FFT blocks, Xilinx CORDIC blocks (for converting to magnitude and phase), and special phase accumulator circuit for mixing to exactly 0 Hz. Upwards of 256 channels can be simultaneously captured and written into a bank of 256 First-In-First-Out (FIFO) memories, with each FIFO corresponding to a channel. Individual channel data can be further processed in the FPGA before being streamed through a 10 GB Ethernet fiber-optic interface to a Linux system. The Linux system runs software written in Python and QT C++ for controlling the ROACH system, capturing data, and processing data.

FPGA-based Volleyball Player Tracker

The significant challenge facing sport science is how to grasp the flow of the game and analyze the situation of amatch. The use of information technology will facilitate to achieve the goal. The technical issues from the practical application perspective can be classified into three main points: computation speed, system size and complex data analysis considering the accuracy. In this paper, for accelerating image recognition and object tracking, we propose a one-dimensional data pipeline architecture on a field-programmable gate array (FPGA). It satisfies both of high-speed streaming computation and small-sized circuits by considering spatiotemporal data dependence. Volleyball games have been chosen as a target application. The proposed system will identify the position of six volleyball players within real time. The design on an FPGA includes pre-processing, color filtering, digitalization, noise reduction, template matching, and so on. The design was implemented and evaluated on Atlys Spartan-6 FPGA Trainer Board with one XILINX Spartan-6 LX45 FPGA. The computational performance achieves 100 frames per second at SVGA 800 by 600 pixel resolution. And our design has good scalability; the performance can easily be enhanced when the larger FPGA is used. The proposed system is also compact, which is composed of one Atlys board and one Atlys VmodCAM stereo-camera board. The average-accuracy rates of pregame situation and during a match are 87.1% and 65.7%, respectively. Since the input is streaming data, we can improve the accuracy by considering the previous and the next frames. They could be improved to 90.4% and 72.2%, respectively, when we adopt template matching with a moving average filter.

Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs

Large field-programmable gate array (FPGA) systems with multiple dice connected by a silicon interposer are now commercially available. However, many questions remain concerning their key architecture parameters and efficiency, as the signal count between dice is reduced and the delay between the dice is increased compared with a monolithic FPGA. We modify the versatile place and route (VPR) to target interposer-based FPGAs and investigate placement and routing changes and incorporating partitioning into the flow to improve results. Our best computer-aided design (CAD) flow reduces the routing demand for interposer FPGAs with realistic connectivity between dice by 47% and improves the circuit speed by 13% on average. Architecture modifications to add routing flexibility when crossing the interposer are very beneficial and improve routability by a further 11%. With these CAD and architecture enhancements, we find that if an interposer supplies (between dice) 20% of the routing capacity that the normal (within-die) FPGA routing channels supply, there is only a modest impact on circuit routability. Smaller interposer-routing capacities do impact routability; however, minimum channel width increases by 70% when an interposer supplies only 10% of the within-die routing. The interposer also impacts delay, increasing circuit delay by 11% on average for a 1-ns interposer signal delay and a two-die system.

Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses

We propose embedding networks-on-chip (NoCs) on field-programmable gate-arrays (FPGAs) to implement system-level communication. Amongst other benefits, this can alleviate the current challenge of connecting the FPGA’s fabric to high-speed I/O and memory interfaces, which are a crucial component of FPGA designs. Our mixed and hard embedded NoCs add only $\sim 1$ % area to large FPGAs and can run much faster than the core logic, thus keeping up with the speed of I/O and memory interfaces. A detailed power analysis, per NoC component, shows that routers consume $14\times $ less power when implemented hard compared with soft, and whether hard or soft most of the router’s power is consumed in the input modules for buffering. For complete systems, hard NoCs consume $4\times $ smaller, and uses 23% less energy when implemented using the hard NoC even though it is only 43% utilized.

The Central Logic Board for the KM3NeT detector: Design and production

The KM3NeT deep sea neutrino observatory will include a very large number of multi-Photomultiplier (PMT) optical modules (DOM) to detect the Cherenkov light generated by secondary particles produced in neutrino interactions. The Central Logic Board (CLB) has been developed to acquire timing and amplitude information from the PMT signals, implementing time-to-digital conversion (TDC) with time over threshold (TOT) technique. The board is also used to configure all the DOM subsystems, to assist in the DOM position and orientation, calibration and to monitor temperature and humidity in the DOM itself. All the collected data are transmitted to shore using a wide-bandwidth optical network. Moreover, through the optical network, all the DOMs are kept synchronized in time within 1ns precision using the White Rabbit (WR) Precision Time Protocol (PTP) over an Ethernet connection. A large Field Programmable Gate Array (FPGA) has been adopted to implement all the specifications witht the requested performances. The CLB will be also used in the base container of the detection unit (DU) to set-up and monitor all the requested functionalities: in this scenario a dedicated firmware and software will be deployed on board. The design has been started in early 2013 and several prototypes have been developed. After deep test carried on in different EU laboratories, the final mass production batch of 600 boards has been ordered and built: all the CLB are now ready for integration in the DOMs and base containers. The first two KM3NeT DU will be deployed in summer 2015 and all other units are in advanced stage of integration.

Design of Low Cost Sigma-Delta Analog-to- Digital Converter for Audio Applications

FPGA (Field-Programmable Gate Array) based solutions in consumer electronics have gained popularity due to low cost and high performance. The time-to market is also shorter and the financial risk is lower compared to ASIC (Application Specific Integrated Circuit). One component that is missing in a low-cost FPGA is the ability to convert an analog signal to its digital counterpart. The aim of this paper is to implement an ADC (Analog-to- Digital Converter) for audio applications using external components together with an FPGA (Field- Programmable Gate Array). The focus is on making the ADC low-cost and it is desirable to achieve 16-bit resolution at 48 KS/s. Since large FPGA’s have numerous I/O-pins, there are usually some unused pins and logic available in the FPGA that can be used for other purposes. This is taken advantage of, to make the ADC as low-cost as possible. This paper presents two types of converters an Σ- ∆ (Sigma-Delta) converter with a first order passive loop-filter and an Σ-∆ converter with a second order active loop-filter. The solutions have been designed on a PCB (Printed Circuit Board) with a Xilinx Spartan FPGA. Both solutions take advantage of the LVDS (Low-Voltage-Differential-Signaling) input buffers in the FPGA. First converter achieves a peak SNDR (Signal-to-noise-and-distortion-ratio) of 62.3 dB (ENOB (Effective number of bits10.06 bits)and it is very low-cost but is not suitable for high-precision audio applications. Second converter achieves a peak SNDR of 80.3 dB (ENOB 13.04) and the cost is more comparatively first one but it is more suitable for mono audio and for stereo audio applications.

A Building Block for Nuclear Medicine Imaging Systems Data Acquisition

Adapting acquisition electronics to new detector designs has often led to complications and compromises. As we developed depth-of-interaction detector designs based on both discrete crystal arrays (dMiCE) and monolithic crystals (cMiCE) concepts, we found that our previous electronics design was inadequate to the task and launched a design effort we have termed our Phase II electronics. The system is based on a basic card design (the Phase II board) that has a large field programmable gate array (FPGA) with sufficient static RAM to support a variety of pulse processing algorithms our group has developed-including timing estimation, pulse integration with pileup correction, and statistical estimation of the event location in the detector. Here we report on the initial development and testing of the Phase II digital board as a basic building block for data acquisition systems.

EVALUATION STUDY OF SYSTOLIC ARRAY PROCESSORS OPTIMIZATION AND MAPPING ON k-LUT FPGA DEVICES

This paper analyzes the design automation of embedded Systolic Array Processors (SAPs), into large scale Field Programmable Gate Array (FPGA) devices. SAPs are hardware implementations of a class of iterative, high-level language algorithms, for applications where the high-speed of processing has the principal meaning of a design. Embedding SAPs onto FPGAs is a complex process. The optimization phase in this process reduces the SAP significantly, thus less FPGA area is occupied by the embedded design, without any loss in the final performance. The present paper examines the effect of Projection Vectors (PVs) and Task Scheduling Vectors (TSVs) on the optimization process. Two optimization approaches are examined, namely technology mapping using FlowMap and Flowpack algorithms and optimization via logic synthesis using Xilinx Synthesis Tool. The multiplication of matrices, with entries being up to 32-bit integer vectors, has been taken as a sample space for the experiments conducted. The results, confirm that the selection of PV and TSV greatly affects the number of input/output signal connections of the FPGA, while the selection of an optimization approach affects the final number of logic resources occupied on the targeted device.

FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network

In order to protect “data-at-rest” in storage area networks from the risk of differential power analysis attacks without degrading performance, a high-throughput masked advanced encryption standard (AES) engine is proposed. However, this engine usually adopts the unrolling technique which requires extremely large field programmable gate array (FPGA) resources. In this brief, we aim to optimize the area for a masked AES with an unrolled structure. We achieve this by mapping its operations from to as much as possible. We reduce the number of mapping [ to ] and inverse mapping [ to ] operations of the masked SubBytes step from ten to one. In order to be compatible, the masked MixColumns, masked AddRoundKey, and masked ShiftRows including the redundant masking values are carried over . We also use FPGA block RAM (BRAM) to further reduce hardware resources. Compared with a state-of-the-art design, our implementation reduces the overall area by 36.2% (20.5% is contributed by the main method, and 15.7% is contributed by the BRAM optimization). It achieves 40.9-Gbits/s at 4.5-Mbits/s/slice on the Xilinx XC6VLX240T platform. We have attacked the iterative version of this masked AES in hardware. Results show that none of the bytes can be guessed from the masked AES with the collected 10 000 power traces, but 14 out of 16 bytes can be guessed from the unprotected AES with the same number of traces.

超高速高性能门控型三分幅相机

Aiming at the framing photography frequency of about 108 frame/s or above,a kind of 3-frame framing camera with ultra high-speed and high performance is developed and put into operation.The optical principle of the camera is based on splitting the focused imaging light beam in the field of image space.It features good imaging quality and high light energy efficiency.The lens coupled gated image intensifier with high speed shutter control ability,cooled scientific CCD camera and the high speed controller based on large scale field programmable gate array with system trigger and shutter trigger are the main portions.This framing camera can capture 3frame images with ultrahigh speed of above 3.3×108 frame/s.The minimum exposure time for each image is about 3ns and can be independently setup in a wide range of from several ns to s.The frame interval time can also be adjusted at discretion step from 0ns to second level.The effective image size isΦ25mm and image array is 1 024×1 024.The spatial resolution is about 30lp/mm.The framing camera features good linearity,good response uniformity,and excellent flexibility in applications.

FPGA Implementation of a CORDIC-Based Joint Angle Processor for a Climbing Robot

This paper presents a novel architecture of a joint angle processor for a robot arm. The objective of the proposed coordinate, rotation, digital computer (CORDIC)-based joint angle processor is to provide a hardware solution for computing the inverse kinematic for a robot arm control system. The complicated trigonometry operation is computed by the famous CORDIC algorithm. Simulation results show that the proposed joint angle processor achieves high precision. Moreover, an efficient pipelined architecture for very large scale integration (VLSI) and field programmable gate array (FPGA) implementation is also proposed, this architecture has the advantage of saving hardware cost and power consumption. As a result, the proposed CORDIC-based joint angle processor provides a high speed inverse kinematic computation that assists the main micro-control-unit (MCU) to operate the robot arm in real time. Therefore, the motion of the robot will be very smooth, capable of powering multiple joints at same time and provide smooth walking or climbing motions.

LISA phasemeter development: Advanced prototyping

We present the status of our investigations on the LISA Phasemeter. The new prototype is based on a custom-designed breadboard with four high-speed ADC and two DAC channels, extended readout capabilities and a large FPGA (field programmable gate array). The required main functionalities and performance of the prototype have been demonstrated in laboratory conditions.

Efficient Hardware/Software Implementation of an Adaptive Neuro-Fuzzy System

This paper describes the development of efficient hardware/software (HW/SW) neuro-fuzzy systems. The model used in this work consists of an adaptive neuro-fuzzy inference system modified for efficient HW/SW implementation. The design of two different on-chip approaches are presented: a high-performance parallel architecture for offline training and a pipelined architecture suitable for online parameter adaptation. Details of important aspects concerning the design of HW/SW solutions are given. The proposed architectures have been implemented using a system-on-a-programmable-chip. The device contains an embedded-processor core and a large field programmable gate array (FPGA). The processor provides flexibility and high precision to implement the learning algorithms, while the FPGA allows the development of high-speed inference architectures for real-time embedded applications.

A vertex trigger based on cylindrical multiwire proportional chambers

This article describes the technical implementation and the performance of the z-vertex trigger (CIP2k), which is part of the H1-experiment at HERA. The HERA storage ring and collider was designed to investigate electron (and positron) proton scattering at a center-of-mass energy of 320 GeV. To improve the sensitivity for detecting non-standard model physics and other high momentum transfer phenomena, the HERA ring has been ungraded between 2000 and 2003 to increase the specific luminosity for the experiments. In order to cope with the increased event and background rate the experiments were upgraded, too. The CIP2k trigger system is based on a set of five cylindrical multiwire proportional chambers with cathode pad readout, and allows to distinguish between events induced by beam background and ep-interactions at the first trigger stage. The trigger decision is calculated dead-time free with a latency of 1.5 μ s in parallel to the beam clock at 10.4 MHz. The trigger-logic is realized in large field programmable gate arrays (FPGA) using the hardware description language Verilog. The system is operational since October 2003. It suppresses background events with high efficiency and provides event timing information, as designed.

A novel FPGA-based architecture for Sobel edge detection operator

A novel FPGA-based architecture for Sobel edge detection algorithm has been proposed. The Sobel algorithm is chosen due to its property of providing a differencing as well as noise smoothing operation in the single kernel. Thus, noise sensitivity of first gradient based operations can be avoided by the use of this algorithm. The implementation of edge detection algorithms on a field programmable gate array (FPGA) is motivated by the fact that large memory FPGAs are now available, providing a platform for processing real time algorithms on application-specific hardware with substantially higher performance than programmable digital signal processors (DSPs). This architecture can be used as a building block of a pattern recognition system, autonomous robot navigation, and also as a system for creating an image dazzling effect in multimedia graphics. This architecture is implicitly pipelined to provide a system capable of operating at a clock speed of 99.499 MHz which is a significant improvement over programmable DSPs implementation.

Routability of Network Topologies in FPGAs

A fundamental difference between application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) is that the wires in ASICs are designed to match the requirements of a particular design. Conversely, in an FPGA, the area is fixed and the routing resources exist whether or not they are used. In this paper, we investigate how well several common network topologies map onto a modern FPGA routing fabric. Different multiprocessor network topologies with between 8 and 64 nodes are mapped to a single large FPGA. Except for the fully-connected networks, it is observed that the difference in logic resources used and routing overhead among these topologies is insignificant for the systems tested. Fully-connected networks up to about 22 nodes are also feasible on the same FPGA although the logic and routing utilization clearly grows much faster. The conclusion is that a modern FPGA fabric is very rich in resources and capable of supporting highly interconnected topologies. For systems with a modest number of nodes implemented on current large FPGAs, it is not necessary to use the connectivity-limited topologies typically used for networks-on-chip. Rather, direct point-to-point connections between all communicating nodes can be considered.