Large Cache Research Articles

Cache-Aided Interference Management in Partially Connected Linear Networks

This paper studies caching in (K+L-1) x K partially connected wireless linear networks, where each of the K receivers locally communicates with L out of the K+L-1 transmitters, and caches are at all nodes. The goal is to design caching and delivery schemes to reduce the transmission latency, by using normalized delivery time (NDT) as the performance metric. For small transmitter cache size (any L transmitters can collectively store the database just once), we propose a cyclic caching strategy so that each of every L consecutive transmitters caches a distinct part of each file; the delivery strategy exploits coded multicasting and interference alignment by introducing virtual receivers. The obtained NDT is within a multiplicative gap of 2 to the optimum in the entire cache size region, and optimal in certain region. For large transmitter cache size (any L transmitters can collectively store the database for multiple copies), we propose a modified caching strategy so that every bit is repeatedly cached at consecutive transmitters; the delivery strategy exploits self-interference cancellation and interference neutralization. By combining these schemes, the NDT is optimal in a larger region. We also extend our results to linear networks with heterogeneous receiver connectivity and partially connected circular networks.

Qnm: A Python package for calculating Kerr quasinormal modes, separation constants, and spherical-spheroidal mixing coefficients

$\mathtt{qnm}$ is an open-source Python package for computing the Kerr quasinormal mode frequencies, angular separation constants, and spherical-spheroidal mixing coefficients. The $\mathtt{qnm}$ package includes a Leaver solver with the Cook-Zalutskiy spectral approach to the angular sector, and a caching mechanism to avoid repeating calculations. We provide a large cache of low $\ell, m, n$ modes, which can be downloaded and installed with a single function call, and interpolated to provide good initial guess for root-polishing at new values of spin.

Benefits of Cache Assignment on Degraded Broadcast Channels

Degraded K-user broadcast channels (BCs) are studied when the receivers are facilitated with cache memories. Lower and upper bounds are derived on the capacity-memory tradeoff, i.e., on the largest rate of reliable communication over the BC as a function of the receivers’ cache sizes, and the bounds are shown to match for interesting special cases. The lower bounds are achieved by two new coding schemes that benefit from nonuniform cache assignments . Lower and upper bounds are also established on the global capacity-memory tradeoff, i.e., on the largest capacity-memory tradeoff that can be attained by optimizing the receivers’ cache sizes subject to a total cache memory budget. The bounds coincide when the total cache memory budget is sufficiently small or sufficiently large, where the thresholds depend on the BC statistics. For small cache memories, it is optimal to assign all the cache memory to the weakest receiver. In this regime, the global capacity-memory tradeoff grows by the total cache memory budget divided by the number of files in the system. In other words, a perfect global caching gain is achievable in this regime and the performance corresponds to a system where all the cache contents in the network are available to all receivers. For large cache memories, it is optimal to assign a positive cache memory to every receiver, such that the weaker receivers are assigned larger cache memories compared to the stronger receivers. In this regime, the growth rate of the global capacity-memory tradeoff is further divided by the number of users, which corresponds to a local caching gain. It is observed numerically that a uniform assignment of the total cache memory is suboptimal in all regimes, unless the BC is completely symmetric. For erasure BCs, this claim is proved analytically in the regime of small cache sizes.

Secrecy Capacity-Memory Tradeoff of Erasure Broadcast Channels

This paper derives upper and lower bounds on the secrecy capacity-memory tradeoff of a wiretap erasure broadcast channel (BC) with ${\mathsf{K}}_{w} $ weak receivers and ${\mathsf {K}}_{s} $ strong receivers, where weak receivers and strong receivers have the same erasure probabilities and cache sizes, respectively. The lower bounds are achieved by the schemes that meticulously combine joint cache-channel coding with wiretap coding and key-aided one-time pads. The presented upper bound holds more generally for arbitrary degraded BCs and arbitrary cache sizes. When only weak receivers have cache memories, upper and lower bounds coincide for small and large cache memories, thus providing the exact secrecy capacity-memory tradeoff for this setup. The derived bounds further allow us to conclude that the secrecy capacity is positive even when the eavesdropper is stronger than all the legitimate receivers with cache memories. Moreover, they show that the secrecy capacity-memory tradeoff can be significantly smaller than its non-secure counterpart, but it grows much faster when cache memories are small. This paper also presents a lower bound on the global secrecy capacity-memory tradeoff where one is allowed to optimize the cache assignment subject to a total cache budget. It is close to the best known lower bound without secrecy constraint. For small total cache budget, the global secrecy capacity-memory tradeoff is achieved by assigning all the available cache memory uniformly over all the receivers if the eavesdropper is stronger than all the legitimate receivers, and it is achieved by assigning the cache memory uniformly only over the weak receivers if the eavesdropper is weaker than the strong receivers.

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance , and write failure . Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In this paper, we propose a system-level framework for reliability exploration and characterization of errors’ behavior in STT-MRAM caches. To this end, we formulate the cache vulnerability considering the intercorrelation of the error types including RF, read disturbance, and write failure as well as the dependency of error rates to workloads’ behavior and process variations (PVs). Our analysis reveals that STT-MRAM cache vulnerability is highly workload-dependent and varies by orders of magnitude in different cache access patterns. Our analytical study also shows that this vulnerability divergence significantly increases by PVs in STT-MRAM cells. To take the effects of system workloads and PVs into account, we implement the error types in gem5 full-system simulator. The experimental results using a comprehensive set of multiprogrammed workloads from SPEC CPU2006 benchmark suite on a quad-core processor show that the total error rate in a shared STT-MRAM LLC varies by 32.0× for different workloads. A further 6.5× vulnerability variation is observed when considering PVs in the STT-MRAM cells. In addition, the contribution of each error type in total LLC vulnerability highly varies in different cache access patterns and moreover, error rates are differently affected by PVs. The proposed analytical and empirical studies can significantly help system architects for efficient utilization of error mitigation techniques and designing highly reliable and low-cost STT-MRAM LLCs.

Temperature-Aware DRAM Cache Management—Relaxing Thermal Constraints in 3-D Systems

High bandwidth 3-D-stacked dynamic random access memory (DRAM) has been proposed to address the memory wall in modern systems, especially when it is used as a large last-level cache (LLC). However, stacking DRAM directly on top of the processor significantly impedes the efficiency of cooling, potentially causing thermal issues both in the processor and DRAM. Dynamic thermal management (DTM) based on DRAM temperature can be heavily intrusive because the normal working temperature for DRAM is lower than the processor temperature limit. This paper shows that in many cases it is better to disable hot portions of the cache rather than apply DTM and slow down the processor. Three temperature-aware cache management mechanisms are proposed to decrease the performance impact of DTM on 3-D systems. Our experiments show these techniques can improve the performance of DRAM-targeted DTM by 26.1% on average which make 3-D systems more practical for the future high-performance computing.

Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design

In the era of short channel length, Dynamic Thermal Management (DTM) has become a challenging task for the architects and designers engineering modern Chip Multi-Processors (CMPs). Ever-increasing demand of processing power along with the developed integration technology produces CMPs with high power density, which in turn increases effective chip temperature. This increased temperature leads to increase in the reliability issues for the chip-circuitry with significant increment in leakage power consumption. Recent DTM techniques apply DVFS or Task Migration to reduce temperature at the cores, the hottest on-chip components, but often ignore the on-chip hot caches. To commensurate the high data demand of these cores, most of the modern CMPs are equipped with large multi-level on-chip caches, out of which on-chip Last Level Caches (LLCs) occupy the largest on-chip area. These LLCs are accounted for their significantly high leakage power consumption that can also potentially generate on-chip hotspots at the LLCs similar to the cores. As power consumption constructs the backbone of heat dissipation, hence, this work dynamically shrinks cache size while maintaining performance constraint to reduce LLC leakage, primarily. These turned-off cache portions further work as on-chip thermal buffers for reducing average and peak temperature of the CMP without affecting the computation. Simulation results claim that, at a minimal penalty on the performance, proposed cache-based thermal management having 8MB centralised multi-banked shared LLC gives around 5°C reduction in peak and average chip temperature, which are comparable with a Greedy DVFS policy.

Comparison of the capabilities of GPU clusters and general-purpose supercomputers for solving 3D inverse problems of ultrasound tomography

This study focuses on developing the algorithms for solving 3D inverse problems of ultrasound tomography using GPU clusters and general-purpose supercomputers. The computing capabilities of these supercomputer architectures in application to wave tomography are compared via numerical simulations.Parallel gradient-based iterative algorithms designed to solve coefficient inverse problems for the wave equation are proposed. We show that layer-by-layer wave tomography can be efficiently performed using both CPU- and GPU-based supercomputers. Solving 3D coefficient inverse problems is much more computationally expensive. A general-purpose (CPU-based) system capable of reconstructing 3D images should be equipped with either a sufficient number of memory access channels or a large number of computing cores with large cache memory and high-speed communication network. Such a system would be very large and expensive. Therefore, the most promising solution is to develop dedicated GPU-based supercomputers.From the applications perspective, this study focuses on problems of developing ultrasound tomography devices for breast cancer diagnosis. Computer simulations show that a GPU cluster capable of performing 3D image reconstruction within reasonable time fits in a single rack and can be incorporated into medical ultrasound tomography facilities.

Energy minimization in the STT-RAM-based high-capacity last-level caches

Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches (L3Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM L3Cs. In this paper, we present an integer linear programming (ILP) formulation which minimizes energy consumption in the STT-RAM-based L3C exploiting the row buffer locality and the prominent features of STT-RAM. Since ILP solvers may not achieve the better result in a reasonable time, we propose a sub-optimal algorithm that obtains the results in a polynomial time. Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art.

REACT: Read/Write Error Rate Aware Coding Technique for Emerging STT-MRAM Caches

Spin-transfer torque magnetic RAMs (STT-MRAMs) are the most promising alternative for static random-access memories in large last-level on-chip caches due to their higher density and near-zero leakage power. However, the reliability of STT-MRAMs is threatened by high probability of read disturbance and write failure . Both read disturbance and write failure, which cause a soft error in the cache cells, have an asymmetric behavior. Read disturbance occurs only in STT-MRAM cells storing “1” value, and write failure error rate in a $0\rightarrow 1$ transition is much higher than that in a $1\rightarrow 0$ transition. In this paper, we propose Read/write Error-rate Aware Coding Technique (REACT) to improve the reliability of the emerging STT-MRAM caches. REACT decreases the read disturbance and write failure rates by reducing the total number of “1”s and $0\rightarrow 1$ transitions on a cache block update. Our simulation results show that REACT reduces the probability of read disturbance and write failure up to 58% and 71%, respectively. These improvements are achieved by imposing negligible area, power, and performance overheads (less than 1%).

FOS: a low-power cache organization for multicores

The cache hierarchy of current multicore processors typically consists of one or two levels of private caches per core and a large shared last-level cache. This approach incurs area and energy wasting due to oversizing the private cache space, data replication through the inclusive cache levels, as well as the use of highly set-associative caches. In this paper, we claim that although this is the commonly adopted approach, it presents important design issues that can be addressed by a more energy efficient organization. This work proposes Flat On-chip Storage (FOS), a novel cache organization that, aimed at addressing energy and area on low-power processors, resolves the mentioned issues. For this purpose, FOS combines L2 and L3 cache levels into a single one, organized as a flat space, and composed of a pool of private small cache slices. These slices are initially powered off to save energy, and they are powered on and assigned to cores provided that the system performance is expected to improve. To provide fast and uniform access from the private L1 caches to the FOS’s cache slices, multiple architectural challenges are overcome, which entails the design of a custom optical network-on-chip. Experimental results show that FOS achieves significant energy savings on both static and dynamic energy over conventional cache organizations with the same storage capacity. FOS static energy savings are as much as 60% over an electrically connected shared cache; these savings grow up to 75% compared to optically connected baselines. Moreover, despite deactivating part of the cache space, FOS achieves similar performance values as those achieved by conventional approaches.

Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads

Inexpensive DRAMs have created new opportunities for in-memory data analytics. However, the major bottleneck in such systems is high memory access latency. Traditionally, this problem is solved with large cache hierarchies that only benefit regular applications. Alternatively, many data-intensive applications exhibit irregular behavior. Hardware multithreading can better cope with high latency seen in such applications. This article implements a multithreaded prototype (MTP) on FPGAs for the relational selection operator that exhibits control flow irregularity. On a standard TPC-H query evaluation, MTP achieves a bandwidth utilization of 83%, while the CPU and the GPU implementations achieve 61% and 64%, respectively. Besides being bandwidth efficient, MTP is also 14.2× and 4.2× more power efficient than CPU and GPU, respectively.

Cost‐efficient high throughput capture of museum arthropod specimen DNA using PCR‐generated baits

Abstract Gathering genetic data for rare species is one of the biggest remaining obstacles in modern phylogenetics, particularly for megadiverse groups such as arthropods. Next generation sequencing techniques allow for sequencing of short DNA fragments contained in preserved specimens >20 years old, but approaches such as whole‐genome sequencing are often too expensive for projects including many taxa. Several methods of reduced representation sequencing have been proposed that lower the cost of sequencing per specimen, but many remain costly because they involve synthesizing nucleotide probes and target hundreds of loci. These datasets are also frequently unique for each project and thus generally incompatible with other similar datasets. Here, we explore utilization of in‐house generated DNA baits to capture commonly utilized mitochondrial and ribosomal DNA loci from insect museum specimens of various ages and preservation types without the a priori need to know the sequence of the target loci. Both within species and cross‐species capture are explored, on preserved specimens ranging in age from one to 54 years old. We found most samples produced sufficient amounts of data to assemble the nuclear ribosomal rRNA genes and near complete mitochondrial genomes and produce well‐resolved phylogenies in line with expected results. The dataset obtained can be straightforwardly combined with the large cache of existing Sanger‐sequencing‐generated data built up over the past 30 years and targeted loci can be easily modified to those commonly used in different taxa. Furthermore, the protocol we describe allows for inexpensive data generation (as low as ~$35/sample), of at least 20 kilobases per specimen, for specimens at least as old as ~1965, and can be easily conducted in most laboratories. If widely applied, this technique will accelerate the accurate resolution of the Tree of Life especially on non‐model organisms with limited existing genomic resources.

Cache-Aware Real-Time Virtualization for Clustered Multi-Core Platforms

With the increasing complexity of recent autonomous platforms, there is a strong demand to better utilize system resources while satisfying stringent real-time requirements. Embedded virtualization is an appealing technology to meet this demand. It enables the consolidation of real-time systems with different criticality levels on a single hardware platform by enforcing temporal isolation. On multi-core platforms, however, shared hardware resources, such as caches and memory buses, weaken this isolation. In particular, due to the resulting cache interference, a large last-level cache in recent processors can easily jeopardize the timing predictability of real-time tasks due to cache interference. While researchers in the real-time systems community have developed solutions to tackle this problem, existing cache management schemes reveal two major limitations when used in a clustered multi-core embedded system. The first is the cache co-partitioning problem, which can lead to wrong cache allocation and cache underutilization. The second is the cache interference of inter-virtual-machine (VM) communication because prior work has considered only independent tasks. This paper presents a cluster-aware real-time cache allocation scheme to address these problems. The proposed scheme takes into account the cluster information of the system, and finds the cache allocation that satisfies the timing and memory requirements of tasks. The scheme also maximizes slack time to meet task deadline, which brings flexibility and resilience to unexpected events. Tasks using inter-VM communication are also provided with guaranteed blocking time and cache isolation. We have implemented a prototype of our scheme on an Nvidia TX2 clustered multi-core platform and evaluated the effectiveness of our scheme over cluster-unaware approaches.

“Useful Information Turned into Something Useless”: Archival Silences, Imagined Records, and Suspicion of Mediated Information in the JFK Assassination Collection

The controversies, beliefs, and arguments surrounding the assassination of John F. Kennedy in November 1963 are classics in the canon of conspiracy theories. In October and November 2017, a large cache of documents was declassified and made available to the public through the National Archives and Records Administration’s (NARA) website. A small community of researchers coalesced soon after on reddit.com. When these users encounter silences, they often react to them with a certain level of suspicion towards NARA, its archivists, or the originating institution. I call this suspicion of mediated information. It is entangled with, and comes about as a result of, the notoriety and contested nature of the JFK assassination and its aftermath, the strength of the impossible archival imaginary and the imagined records associated with the JFK Assassination collection, and the nature of the archival silences in the online JFK Assassination Collection. Archivists, particularly those working with collections of conspiratorial significance (the MK-ULTRA documents, collections having to do with UFOs, etc.), should be aware of these sorts of reasoning patterns and how they affect use of the collection and user attitudes towards the collecting institution. The first section of this paper introduces the JFK Assassination Collection, the second goes through the canon of scholarship on conspiracy theories, outlining the new notion of suspicion of mediated information. In section three, I present my theoretical framework—rooted in the notion of Michel-Rolphe Trouillot’s “archival silences,” and Anne Gilliland and Michelle Caswell’s imagined records and impossible archival imaginaries. Section four outlines method, and section five consists of data and discussion. This paper constitutes preliminary research into the area, and will be built upon in later research.

Response: Postexceptionalist Puritanism: Rocking the Foundations

Response: Postexceptionalist Puritanism: Rocking the Foundations

An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches

Spin-Transfer Torque RAM (STT-RAM) has attracted attention as a key element for the Last-Level Cache (LLC) of a future microprocessor. Since STT-RAM has a higher density than SRAM and non-volatility, STT-RAM can contribute to building the cache memory with a larger capacity and a less static energy. However, since STT-RAM changes its magnetization state in the case when storing data, the energy cost of write access requests for an STT-RAM LLC is more expensive than that of an SRAM LLC. As a result, the total energy consumption of the STT-RAM LLC for write-intensive applications may increase. To solve this problem, this paper proposes an Adjacent-Line-Merging Writeback Scheme. Since a larger cache line of an STT-RAM cache can contribute to the reduction in the write energy cost per byte, the upper-level cache merges two adjacent small lines to one large line, and then writes the merged line back to the STT-RAM LLC. Moreover, the larger line size for the LLC leads to a reduction in the static energy cost. The evaluation results show that the proposed scheme can reduce the energy consumption of the STT-RAM LLC by up to 26, and 9.3 percent on average.

On the Convergence of the TTL Approximation for an LRU Cache under Independent Stationary Request Processes

The modeling and analysis of an LRU cache is extremely challenging as exact results for the main performance metrics (e.g., hit rate) are either lacking or cannot be used because of their high computational complexity for large caches. As a result, various approximations have been proposed. The state-of-the-art method is the so-called TTL approximation, first proposed and shown to be asymptotically exact for IRM requests by Fagin [13]. It has been applied to various other workload models and numerically demonstrated to be accurate but without theoretical justification. In this article, we provide theoretical justification for the approximation in the case where distinct contents are described by independent stationary and ergodic processes. We show that this approximation is exact as the cache size and the number of contents go to infinity. This extends earlier results for the independent reference model. Moreover, we establish results not only for the aggregate cache hit probability but also for every individual content. Last, we obtain bounds on the rate of convergence.

Communists and American Farmers in the 1920s

On 28 April 1921, New York police and Bureau of Investigation agents raided a Greenwich Village studio, arresting several people and seizing a large cache of Communist documents. The raid was repor...

An optimized blockchain solution for the IBM z14

Blockchain is a technology that has been available for several years and has already had several generations. Multiple implementations exist. In this paper, we describe how one of them, the Hyperledger Fabric, is used today to demonstrate the wide usage of the technology for multiple markets beyond finance and cryptocurrency. The use cases highlight the relevance of security—due to the type of data and the distributed foundation of blockchain—and of system performance to enable the use cases in production. Security and performance are the base for the architecture of blockchain on the IBM LinuxONE systems. The Secure Service Container prevents tampering, and the cryptocard usage hardens the solution—and the performance optimization in the compiler, cryptoinstructions, and large caches provides the performance. These optimizations have been further extended with the IBM z14 beyond previous IBM Z generations. In this paper, we describe how a cluster topology is used to implement a high-availability service that scales dynamically from small networks to large ones using the hot plug capabilities of the IBM LinuxONE systems.