Large ATM Research Articles

A GIS Based Approach to Manage Spatial Distribution and Location of Financial Services: A Case Study of ATM Services

Location convenience is an important factor when customers select a financial institution. To stay competitive, banks usually attempt to increase convenience (be as close as possible to customers) by expanding their branch or ATM networks. Using GIS in the arena of finance can be very supportive and cost effective to facilitate location based decisions for financial institutions. For business expansion planning, banks need location-relevant data, and cost effective site analysis to select a new bank branch or ATM location confidently and reliably in a shorten-time cycle. When banks plan to open new branches, they need to consider the data such as the concentration of commercial areas, traffic patterns, workplaces or living places of customers whose demographics and purchase behavior match banks’ target customer profiles. In this research, GIS-based approach has been developed to identify suitable location for an ATM network in Perspective of Bangladesh. The newly established banks those have not set up ATM network yet or have very small scale ATM services network can expand their banking services through acquiring partners from existing ATM network of other Banks and simultaneously can construct new ATMs in the most suitable unserved areas. This is how these banks can expand their ATM network more rapidly with a less establishment cost. Also banks, those have large ATM network with some unserved areas, can expand their existing network by reaching to the customers’ convenience locations. The paper recommends that the analysis using GIS to find most suitable locations for ATM is better applicable for other cities and towns. JBIP, Vol. 9, 2016 (Printed in April 2018), pp. 125-140

Architectural choices in large scale ATM switches

The rapid development of Asynchronous Transfer Mode technology in the last 10-15 years has stimulated renewed interest in the design and analysis of switching systems, leading to new ideas for system designs and new insights into the performance and evaluation of such systems. As ATM moves closer to realizing the vision of ubiquitous broadband ISDN services, the design of switching systems takes on growing importance. This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.

The ZFHX3 (ATBF1) transcription factor induces PDGFRB, which activates ATM in the cytoplasm to protect cerebellar neurons from oxidative stress

Ataxia telangiectasia (A-T) is a neurodegenerative disease caused by mutations in the large serine-threonine kinase ATM. A-T patients suffer from degeneration of the cerebellum and show abnormal elevation of serum alpha-fetoprotein. Here, we report a novel signaling pathway that links ATM via cAMP-responsive-element-binding protein (CREB) to the transcription factor ZFHX3 (also known as ATBF1), which in turn promotes survival of neurons by inducing expression of platelet-derived growth factor receptor β (PDGFRB). Notably, AG1433, an inhibitor of PDGFRB, suppressed the activation of ATM under oxidative stress, whereas AG1433 did not inhibit the response of ATM to genotoxic stress by X-ray irradiation. Thus, the activity of a membrane-bound tyrosine kinase is required to trigger the activation of ATM in oxidative stress, independent of the response to genotoxic stress. Kainic acid stimulation induced activation of ATM in the cerebral cortex, hippocampus and deep cerebellar nuclei (DCN), predominately in the cytoplasm in the absence of induction of γ-H2AX (a marker of DNA double-strand breaks). The activation of ATM in the cytoplasm might play a role in autophagy in protection of neurons against oxidative stress. It is important to consider DCN of the cerebellum in the etiology of A-T, because these neurons are directly innervated by Purkinje cells, which are progressively lost in A-T.

Growth of persistent foci of DNA damage checkpoint factors is essential for amplification of G1 checkpoint signaling

Several DNA damage checkpoint factors form nuclear foci in response to ionizing radiation (IR). Although the number of the initial foci decreases concomitantly with DNA double-strand break repair, some fraction of foci persists. To date, the physiological role of the persistent foci has been poorly understood. Here we examined foci of Ser1981-phosphorylated ATM in normal human diploid cells exposed to 1 Gy of X-rays. While the initial foci size was approximately 0.6 μm, the one or two of persistent focus (foci) grew, whose diameter reached 1.6 μm or more in diameter at 24 h after IR. All of the grown persistent foci of phosphorylated ATM colocalized with the persistent foci of Ser139-phosphorylated histone H2AX, MDC1, 53BP1, and NBS1, which also grew similarly. When G0-synchronized normal human cells were released immediately after 1 Gy of X-rays and incubated for 24 h, the grown large phosphorylated ATM foci (≥1.6 μm) were rarely (av. 0.9%) observed in S phase cells, while smaller foci (<1.6 μm) were frequently (av. 45.9%) found. We observed significant phosphorylation of p53 at Ser15 in cells with a single grown phosphorylated ATM focus. Furthermore, persistent inhibition of foci growth of phosphorylated ATM by an ATM inhibitor, KU55933, completely abrogated p53 phosphorylation. Defective growth of the persistent IR-induced foci was observed in primary fibroblasts derived from ataxia-telangiectasia (AT) and Nijmegen breakage syndrome (NBS) patients, which were abnormal in IR-induced G1 checkpoint. These results indicate that the growth of the persistent foci of the DNA damage checkpoint factors plays a pivotal role in G1 arrest, which amplifies G1 checkpoint signals sufficiently for phosphorylating p53 in cells with a limited number of remaining foci.

ATM Surcharge Bans and Bank Market Structure: The Case of Iowa and its Neighbors

Abstract It is frequently claimed that high ATM surcharges actually attract customers to the banks that impose them, particularly if they operate large ATM networks. By exploiting as “natural experiments” two events associated with the lifting of surcharge bans in Iowa and in the states that neighbor Iowa, this paper seeks to test for the implications of this phenomenon as it applies to the market shares of banking institutions and to several aspects of market structure. Consistent with predictions, results of “difference-in-difference” analyses suggest that the retail account shares of larger market participants increased relative to those of smaller competitors, market concentration increased, and the number of market competitors decreased after the lifting of surcharge bans – all relative to what would have occurred had there been no change in authority to surcharge.

ATM surcharge bans and bank market structure: The case of Iowa and its neighbors

It is frequently claimed that high ATM surcharges actually attract customers to the banks that impose them, particularly if they operate large ATM networks. By exploiting as “natural experiments” two events associated with the lifting of surcharge bans in Iowa and in the states that neighbor Iowa, this paper seeks to test for the implications of this phenomenon as it applies to the market shares of banking institutions and to several aspects of market structure. Consistent with predictions, results of “difference-in-difference” analyses suggest that the retail account shares of larger market participants increased relative to those of smaller competitors, market concentration increased, and the number of market competitors decreased after the lifting of surcharge bans – all relative to what would have occurred had there been no change in authority to surcharge.

ATM Surcharge Bans and Bank Market Structure: The Case of Iowa and its Neighbors

It is frequently claimed that high ATM surcharges actually attract customers to the banks that impose them, particularly if they operate large ATM networks. By exploiting as "natural experiments" two events associated with the lifting of surcharge bans in Iowa and in the states that neighbor Iowa, this paper seeks to test for the implications of this phenomenon as it applies to the market shares of banking institutions and to several aspects of market structure. Consistent with these implications, results of "difference-in-difference" analyses suggest that the shares of larger market participants increase, the shares of smaller market participants decrease, market concentration increases, and the number of market competitors decreases after the lifting of surcharge bans.

Adaptive crankback schemes for hierarchical QoS routing in ATM networks

To reduce routing information and achieve scalability in large ATM networks, ATM Private Network-to-Network Interface (PNNI) adopts hierarchical routing. For efficient routing, a large ATM network is decomposed into subnetworks called Peer Groups (PG), which advertise aggregated routing information only. Because of lack of precision in the aggregated information, a call set up message on a chosen route can be rejected. When an ATM node discovers that a call set up message cannot proceed due to insufficient resources, a back-tracking procedure called ‘crankback’ is initiated against call blocking. Although crankback reduces blocking probability, it also causes additional overhead, such as longer setup delay. Consequently, this study proposes two approaches to reduce crankback overhead. The first approach adds extra information to the setup message, referred to as Crankback Information Stack (CIS), to reduce crankback overhead. Meanwhile, the other approach, referred to as Cost Threshold (CT), uses the aggregated path cost and the cost information of previously rejected call setup message to determine whether call setup should be tried on the next alternate path. The simulation results herein demonstrate that both of the proposed approaches significantly reduce crankback overhead, while the combination of the CIS and CT approach achieves further improvement.

Efficient hierarchical QoS routing in ATM networks

For reducing network information to achieve scalability in large ATM networks, ATM Private Network-to-Network Interface (PNNI) adopts hierarchical routing. Consequently, although routing complexity is significantly reduced, numerous issues in PNNI routing require further study to achieve more efficient, accurate, scalable, and QoS-aware routing. Several methods are adopted herein to achieve efficient, scalable, and QoS-aware ATM PNNI routing. First, an efficient aggregation scheme, referred to as Asymmetric Simple, is proposed. The aggregated routing information includes available bandwidth, delay and cost. Second, two approaches for defining link costs are investigated, namely, the Markov Decision Process (MDP) approach and the Competitive On-Line (COL) routing approach, and these are compared with the Widest Path (WP) approach. Finally, a dynamic update policy, referred to as the dynamic cost-based update (DCU) policy, is proposed to improve the accuracy of the aggregated information and the performance of hierarchical routing, while decreasing the frequency of re-aggregation and information distribution. Simulation results demonstrate that the proposed Asymmetric Simple aggregation scheme yields very good network utilization while significantly reducing the amount of advertised information. Between these two link cost functions, the MDP approach provides a systematic method of defining call admission function and yields better network utilization than the COL approach. The proposed DCU policy also yields an enhanced network utilization while significantly reducing the frequency of re-aggregation and the amount of distributed aggregation information.

A performance model of partial packet discard and early packet discard schemes in ATM switches

In this paper, we develop a concise performance model of partial packet discard (PPD) and early packet discard (EPD) schemes in ATM switches. We study the performance of PPD and EPD with heterogeneous traffic sources. The sources included Poisson, and ON–OFF with long-tailed sojourn time distribution, which is approximated by a hyperexponential distribution. The fairness of EPD is investigated. We automatically generate and numerically solve the underlying Markov chain using a high-level graphical paradigm known as the stochastic reward net. Our numerical results reveal that: (1) the benefit of PPD and EPD is not significant when the queuing system is underloaded with Poisson sources; (2) PPD and EPD can increase the goodput when the system is overloaded or loaded with ON–OFF sources; (3) in All Poisson case, PPD and EPD provide nearly fair service to the sources; (4) the ON–OFF source gets higher goodput than the Poisson source. Because the burstiness of a source will be alleviated by the statistical multiplexing of ATM switches, the ON–OFF source may be viewed as the source that just enters the network, and the Poisson source may be viewed as the source being far away from the network node we are considering and has been regulated and smoothed by the switches it traversed. Therefore, the queuing system with EPD algorithm gives a higher goodput to the sources near it. And the sources far away from the system will have lower goodput. One of our principal conclusions is that per-VC-based scheme is not needed at the core of large ATM networks because the traffic is less bursty at the core of the networks and PPD and EPD are fair under this kind of environment. A per-VC-based scheme may be used at the edge of the ATM cloud. Such a configuration can make the core of the ATM network work at high speed.

A new queuing strategy for large scale ATM switches

In this article, different buffering techniques used to solve the contention problem in ATM switching architectures are compared. Then, the buffer requirements needed to achieve a given quality of service (QoS) is determined. Based on the results, we propose a combined central and output queuing (CCOQ) technique to be used in designing large-scale ATM switches for high-speed networks.

Parallel shared-memory simulator performance for large ATM networks

A performance comparison between an optimistic and a conservative parallel simulation kernel is presented. Performance of the parallel kernels is also compared to a central-event-list sequential kernel. A spectrum of ATM network and traffic scenarios representative of those used by ATM networking researchers are used for the comparison. Experiments are conducted with a cell-level ATM network simulator and an 18-processor SGI PowerChallenge shared-memory multiprocessor. The results show the performance advantages of parallel simulation ove r sequential simulation for ATM networks. Speedups of 4-5 relative to a fast sequential kernel are achieved on 16 processors for several large irregular ATM benchmark scenarios and the optimistic kernel achieves 2 to 5 times speedup on all 7 benchmarks. However, the relative performance of the two parallel simulation kernels is dependent on the size of the ATM network, the number of traffic sources, and the traffic source types used in the simulation. For some benchmarks the best single point performance is provided by the conservative kernel even on a single processor. Unfortunately, the conservative kernel performance is susceptible to small changes in the modeling code and is outperformed by the optimistic kernel on 5 of the 7 benchmarks. The optimistic parallel simulation kernel thus provides most robust performance, but its speedup is limited by the overheads of its implementation, which make it approximately half the speed of the sequential kernel on one processor.

Performance of a large multicast ATM switch

In this paper, we present the design of a large self-routing multicast ATM switch. The switch consists of a sorting network followed by a 3-stage routing network. We first present a simple design of a large sorting network built using small sized shared memory that can be used as a building block for a large sorting network. Small sized shared memory is also used in the 3-stage routing network making the switch modular and easy to implement using current VLSI technology. As the network uses shared memory modules, multicasting functionality is easily built into the network. The performance of the proposed network is compared with an equivalent completely shared memory switch using computer simulations under bursty traffic model. The results show that the proposed network has better performance in terms of cell loss ratio than the completely shared memory switch under moderate to heavy traffic load (0.6 ≤ effective offered load ≤ 1.2). Furthermore, multicast cell delays are drastically improved.

Large scale enterprise ATM node with per-VC traffic control

On the backbone nodes of enterprise networks which handle data and voice traffic, complicated Quality of Service (QoS) capability, transmission efficiency, and high reliability are required. ATM technology satisfies those requirements. We have developed a large scale enterprise ATM node based on the shared buffer switch architecture. In the node, per-VC traffic control functions are implemented at low cost using centralized control of buffer write and read. In this paper, we explain the detail of the per-VC traffic control functions and show the performance results of ABR control using the node.

IBM 8265 ATM Backbone Switch software architecture

The IBM 8265 ATM Backbone Switch is the latest switch in the family of IBM ATM switches, designed for building large scale and reliable ATM network backbones. Two articles on the IBM 8265 ATM Backbone Switch are provided in this journal, describing the hardware architecture and the software architecture separately. This article describes the functions of the ATM Operating System and the ATM Multi-protocol Switched Services that run inside the IBM 8265 ATM switch. The focus is given to issues that are not addressed by the ATM Forum, and extensions that are needed when building ATM networks.

The MainStreetXpress 36190: a scalable and highly reliable ATM core services switch

This paper describes the architecture and some of the main features of the MainStreetXpress 36190 ATM core services switch. This switch has been designed from the start as a fully functional, central office class ATM switch which can be used already today to create the backbone layer for commercial ATM-based multi-service networks. Due to its modular hardware and software architecture, it provides the required flexibility with respect to interface requirements, signalling/control capabilities and service support. The architecture together with the ATM chip set specifically developed for this switch allows to extend the data throughput of the MainStreetXpress 36190 from 5 Gbit/s into the Tbit/s range by just scaling the central switch fabric. The call processing capability can be scaled well into the MBHCA range (Million Busy Hour Call Attempts) by taking advantage of the specifically developed multi-processor control platform. Full redundancy for all central hardware components and optional redundancy for interface boards and external transmission lines is provided. In combination with a comprehensive hardware/software maintenance and recovery concept based on the vast experience with the EWSD line of digital switches these capabilities provide the reliability and availability required for large ATM carrier networks. Together with the full line of MainStreetXpress components – ranging from network terminations and LAN service units via flexible access multiplexers/switches to scalable ATM multi-service switches and a variety of specific server types all controlled by a common network and service management – the MainStreetXpress 36190 provides carriers with the means to realize fully functional, cost effective ATM based multi-service platforms already today.

Mobility management for large private wireless ATM installations

New mobility management protocols that aim to support terminal movement, in wireless ATM Customer Premises Networks (CPN) are presented. The functionality of these protocols consists of the procedures for handover (i.e., re-routing of active data connections to a new radio cell) and the procedures for location management (i.e., storing and retrieving the exact location of a mobile terminal). In the considered CPN environment, the ATM switches communicate using the PNNI protocol, the routing functionality of which is used by the mobility management protocols to perform their tasks more efficiently.

Realization of large capacity ATM switches

Large-capacity ATM switches, with switching capacity in excess of 40 Gb/s or 100 Gb/s, are becoming an essential part of network growth. To realize such switches requires technology know-how as well as implementation trade-off considerations. This article provides a system-level exploration of large-capacity ATM switches in terms of switch fabric scalability, cell buffer management, buffer design trade-off, call processing capabilities, and future trends in switch design.

Conservative simulation of load-balanced routing in a large ATM network model

Conservative simulation of load-balanced routing in a large ATM network model

Analysis of large ATM switches using a platform-independent simulation environment

This paper presents a general simulation approach applied to the problem of performance evaluation of large switching fabrics. Experimental results in the form of cell queuing delay and buffer occupancy distributions for switches with up to 2048 inputs and outputs operating under a wide variety of loads are presented. The traditional dilemma between simulation model validity and its run-time where a more general purpose model inevitably results in longer execution times, is eliminated by the introduction of a new parameter: the architecture of the simulation platform. With model validity as an invariant, the simulation platform can range from a sequential computer via shared memory and distributed memory general purpose parallel processors up to a dedicated emulator, on the condition that the software engineering problem has been solved, i.e. that there is a software tool available that automates that task of generating simulation code for various platforms from a single model, taking the characteristics of the platforms (granularity) into account. An analytical model of the class of applications under study gives insight into the influence of machine and problem parameters on simulator run-time performance. Examples of its use for the choice of an optimal parallel architecture for a given problem and of its use for the estimation of application behavior on a given parallel machine architecture are presented.