L2 Cache Size Research Articles

A study on impacts of hardware changes on performance of different multithreading libraries based on Gem5

This paper presents a thorough investigation into the performance of various multithreading libraries on different hardware configurations utilizing gem5. The study compares the performance of commonly-used multithreading libraries, including OpenMP, Pthread, TBB, and Dlib, through several benchmarks representing distinct types of workloads. Key hardware factors that directly affect the performance of each library are identified and analyzed. The research findings provide valuable insights and recommendations for selecting an appropriate multithreading library for a given application and hardware platform. Results indicate that the performance of multithreading libraries is influenced by numerous hardware factors, such as L1 cache size, L1 cache associate, L1 cache replacement policy, number of threads, and memory type. The libraries respond differently to these factors, and the performance variability of each library depends on the nature of the workload. The study offers a detailed analysis and valuable insights into the effects of these hardware factors on each library. This study contributes by presenting a comprehensive comparison of several widely used multithreading libraries across numerous hardware configurations, identifying the key hardware factors that influence the performance of each library, and providing insights and recommendations for selecting an appropriate multithreading library for a given application and hardware platform. Ultimately, the study results can help software developers make informed decisions when selecting a multithreading library and optimizing performance for their applications.

Evaluating Fault-Tolerant Techniques on COTS RISC-V NOEL-V Processor in Zynq UltraScale+ FPGA Under Proton Testing

This work evaluates different fault tolerance techniques on the RISC-V NOEL-V processor synthesized into the SRAM-based Zynq UltraScale+ FPGA under proton testing. We investigate the effect of the cache size on the reliability of the processor and the use of scrubbing combined with triplication, duplication with comparison, and cache refreshing. The design area in SRAM-based FPGAs directly affects the soft error cross section. However, results show that increasing the L1 cache size and using the correct combination of mitigation techniques reduces the overall SEE susceptibility of the RISC-V NOEL-V processor.

Implementation of a direct-addressing based lattice Boltzmann GPU solver for multiphase flow in porous media

GPU accelerated lattice Boltzmann (LB) simulations of multiphase flow in porous media have become a powerful tool to study fluid displacement process in porous media. For porous structures with a very low porosity, indirect-addressing memory access methods are preferred due to significantly reduction of the memory footprint despite that those methods are more difficult to implement and the resulting performance may be more sensible to the computing architectures, such as cache hierarchy and size. The direct-addressing methods are straightforward to implement and are able to archive high throughput when the porosity is large, while the methods become less efficient when the structures are too sparse. Nevertheless, the direct-addressing methods combined with multi-block grid technique are promising for many applications. In this work, we present a hybrid-way to tackle multiphase flow simulations in porous media, where the direct-addressing method is employed for the main LB evolution while the indirect-addressing method is employed for the complex boundary conditions. The CSF-based LB color-gradient multiphase model and the geometry-based wetting model are employed to increase accuracy and stability. Thanks to the utilization of AA-pattern streaming scheme, non-slip boundary condition of arbitrary orientation can be enforced without extra cost. We perform comprehensive analysis of the computational performance of the present solver on NVIDIA GPUs. For typical sandstones, our results show that the present implementation is able to achieve over 1.5 speedup compared with other direct-addressing schemes on V100 and A100, respectively and, particularly, the computational performance of the boundary kernels is greatly increased thanks to the increased L2 cache size of the latest GPUs.

LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager

The vigorous development of high compute-intensive applications has led to the demand for maximizing the concurrency of multicore processors. The best-effort hardware transactional memory(HTM) is an important technology adopted by vendors to improve the potential concurrency of multicore processors, but the HTM implementations on commercial products have some drawbacks for its simplicity and need some further optimizations to enable more exploitation of concurrency. In this article, we propose and evaluate a novel design of HTM, called LosaTM, which can provide a scenario-awareness conflict management strategy. By leveraging the proposed feature of multiple-grained coherency maintenance in the coherence protocol, LosaTM resolves most false conflicts at a half-cache-line granularity. Furthermore, we design a winner/aborter vector conflict management algorithm to improve the efficiency of LosaTM in handling friendly-fire and unfairness competition that we have newly defined. In order to coordinate these integrated conflict management strategies, a scheduling strategy is also proposed to adaptively select the appropriate management according to the specific conflict scenario. We use gem5 to simulate LosaTM in detail on an 8-core tiled CMP system, and the simulation result shows that it only causes 0.7% of the L1 cache size hardware overhead while achieving a 38% average execution time reduction on the native STAMP. The speedup also demonstrates that LosaTM outperforms the state-of-the-art designs in previous works.

Cache blocking strategies applied to flux reconstruction

On modern hardware architectures, the performance of Flux Reconstruction (FR) methods can be limited by memory bandwidth. In a typical implementation, these methods are implemented as a chain of distinct kernels. Often, a dataset which has just been written in the main memory by a kernel is read back immediately by the next kernel. One way to avoid such a redundant expenditure of memory bandwidth is kernel fusion. However, on a practical level kernel fusion requires that the source for all kernels be available, thus preventing calls to certain third-party library functions. Moreover, it can add substantial complexity to a codebase. An alternative to full kernel fusion is cache blocking. But for this to be effective, CPU cache has to be meaningfully big. Historically, size of L1 and L2 caches prevented cache blocking for high-order CFD applications. However in recent years, size of L2 cache has grown from around 0.25 MiB to 1.25 MiB, and made it possible to apply cache blocking for high-order CFD codes. In this approach, kernels remain distinct, and are executed one after another on small chunks of data that can fit in the cache, as opposed to on full datasets. These chunks of data stay in the cache and whenever a kernel requests access to data that is already in the cache, memory bandwidth is conserved. In this study, a data structure that facilitates cache blocking is considered, and a range of kernel grouping configurations for an FR based Euler solver are examined. A theoretical study is conducted for hexahedral elements with no anti-aliasing at p=3 and p=4 in order to determine the predicted performance of a few kernel grouping configurations. Then, these candidates are implemented in the PyFR solver and the performance gains in practice are compared with the theoretical estimates that range between 2.05x and 2.50x. An inviscid Taylor-Green Vortex test case is used as a benchmark, and the most performant configuration leads to a speedup of approximately 2.81x in practice.

PAVER

The massive parallelism present in GPUs comes at the cost of reduced L1 and L2 cache sizes per thread, leading to serious cache contention problems such as thrashing. Hence, the data access locality of an application should be considered during thread scheduling to improve execution time and energy consumption. Recent works have tried to use the locality behavior of regular and structured applications in thread scheduling, but the difficult case of irregular and unstructured parallel applications remains to be explored. We present PAVER , a P riority- A ware V ertex schedul ER , which takes a graph-theoretic approach toward thread scheduling. We analyze the cache locality behavior among thread blocks ( TBs ) through a just-in-time compilation, and represent the problem using a graph representing the TBs and the locality among them. This graph is then partitioned to TB groups that display maximum data sharing, which are then assigned to the same streaming multiprocessor by the locality-aware TB scheduler. Through exhaustive simulation in Fermi, Pascal, and Volta architectures using a number of scheduling techniques, we show that PAVER reduces L2 accesses by 43.3%, 48.5%, and 40.21% and increases the average performance benefit by 29%, 49.1%, and 41.2% for the benchmarks with high inter-TB locality.

A Varying Processor Cache Sets Architecture

Any processor cache has three parameters capacity, line size and associativity. Usually all three are fixed at design time. Algorithms to have variable cache sets are proposed in literature. This paper proposes a method to have variable cache sets logically. The cache comes with fixed sets. The cache is visualized to have logically any number of sets greater than or equal to one. An algorithm for line placement/replacement is proposed in this paper for this model. The proposed model is simulated with SPEC2K benchmarks using Simplescalar Toolkit for two level inclusive set associative cache system. A power saving of 8.4% for L1 cache size 512x4, 17.58% for 1024x4 and 31.3% for 2048x4 is observed compared with traditional set associative cache of same size. A power saving of 7.53% compared with model proposed in literature for L1 size 512x4, 7.64% for 1024x4 and 7.645% for 2048x4 is observed. The L2 cache size is fixed at 2048x8. The average memory access time (AMAT) is found to degrade compared with conventional set associative cache by 19.63% for L1 size of 512x4, 24.68% for 1024x4 and 2048x4. (Abstract)

Fuzzy Logic-Based DSE Engine: Reconfiguration for Optimization of Multicore Architectures

Moore’s law has been one of the reason behind the evolution of multicore architectures. Modern multicore architectures offer great amount of parallelism and on-chip resources that remain underutilized. This is partly due to inefficient resource allocation by operating system or application being executed. Consequently the poor resource utilization results in greater energy consumption and less throughput. This paper presents a fuzzy logic-based design space exploration (DSE) approach to reconfigure a multicore architecture according to workload requirements. The target design space is explored for L1 and L2 cache size and associativity, operating frequency, and number of cores, while the impact of various configurations of these parameters is analyzed on throughput, miss ratios for L1 and L2 cache and energy consumption. MARSSx86, a cycle accurate simulator, running various SPALSH-2 benchmark applications has been used to evaluate the architecture. The proposed fuzzy logic-based DSE approach resulted in reduction in energy consumption along with an overall improved throughput of the system.

Transformer: Run-time reprogrammable heterogeneous architecture for transparent acceleration of dynamic workloads

Heterogeneous architectures face challenges regarding transparent acceleration as well as the allocation of resources to cores and accelerators. The “Transformer”, a run-time reprogrammable, heterogeneous architecture consisting of cores and reconfigurable logic with support for coarse-grained acceleration of the dynamic, unpredictable workloads present in mobile and cloud computing environments, is proposed as a solution. The architecture allows for the run-time instantiation of one or more acceleration functions, present in an on-chip reconfigurable logic, which responds to the demands of compute-intensive software libraries. The hardware controller and software wrapper functions are designed to profile workloads, reprogram the internal logic, and invoke the appropriate acceleration functions. Novel heuristics are derived with respect to the accelerator function scheduling. In order to optimize performance and power efficiency, the appropriate system parameters are explored, including the L1 and L2 cache sizes, the accelerator local buffer sizes, as well as the allocation of resources to the cores and accelerators. The simulation results indicate that the Transformer provides significant improvements in terms of performance, up to 14× for single-type workloads and 2.3× for dynamic workloads, as well as energy efficiency, up to 6.9× for various workloads.

The Direct-to-Data (D2D) cache

Modern processors optimize for cache energy and performance by employing multiple levels of caching that address bandwidth, low-latency and high-capacity. A request typically traverses the cache hierarchy, level by level, until the data is found, thereby wasting time and energy in each level. In this paper, we present the Direct-to-Data (D2D) cache that locates data across the entire cache hierarchy with a single lookup. To navigate the cache hierarchy, D2D extends the TLB with per cache-line location information that indicates in which cache and way the cache line is located. This allows the D2D cache to: 1) skip levels in the hierarchy (by accessing the right cache level directly), 2) eliminate extra data array reads (by reading the right way directly), 3) avoid tag comparisons (by eliminating the tag arrays), and 4) go directly to DRAM on cache misses (by checking the TLB). This reduces the L2 latency by 40% and saves 5-17% of the total cache hierarchy energ D2D's lower L2 latency directly improves L2 sensitive applications' performance by 5-14%. More significantly, we can take advantage of the L2 latency reduction to optimize other parts of the micro-architecture. For example, we can reduce the ROB size for the L2 bound applications by 25%, or we can reduce the L1 cache size, delivering an overall 21% energy savings across all benchmarks, without hurting performance.

Temperature Sensing RRAM Architecture for 3-D ICs

3-D integrated circuits, or 3-D ICs, have gained significant attention in the research community over the past few years. This has primarily been motivated by their enhanced power, performance, and functionality over planar CMOS ICs. However, thermal management remains a key challenge in these devices due to the impedance of heat flow that results from die stacking. In this paper, we address this challenge by utilizing a temperature sensing resistive random access memory (TSRRAM) which can generate accurate thermal profiles to gauge the heat distribution within the 3-D IC. The architecture enables each RRAM switching element in the memory die to be used both as a memory bit and a temperature sensor. We simulated our TSRRAM design as an L2 cache for an alpha 21364 processor. We used a customized simulation framework to test the design accuracy and performance over several SPEC2000 CPU benchmarks, and achieved a 2.14 K mean error and an eight-cycle performance overhead with a 4-kB L2 cache size. Furthermore, we show that active sensing methods can be employed to achieve 100% coverage of global hot spot temperatures.

Study of Various Factors Affecting Performance of Multi-Core Processors

Advances in Integrated Circuit processing allow for more microprocessor design options. As Chip Multiprocessor system (CMP) become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single chip. This enables sharing of computation resources that was not previously possible. In addition the virtualization of these computation resources exposes the system to a mix of diverse and competing workloads. On chip Cache memory is a resource of primary concern as it can be dominant in controlling overall throughput. This Paper presents analysis of various parameters affecting the performance of Multi-core Architectures like varying the number of cores, changes L2 cache size, further we have varied directory size from 64 to 2048 entries on a 4 node, 8 node 16 node and 64 node Chip multiprocessor which in turn presents an open area of research on multicore processors with private/shared last level cache as the future trend seems to be towards tiled architecture executing multiple parallel applications with optimized silicon area utilization and excellent performance.

Power/Performance/Thermal Design-Space Exploration for Multicore Architectures

Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better thermal/power scaling (many small cores dissipate less than a large and complex one), and the ease and reuse of design. This paper presents a thorough evaluation of multicore architectures. The architecture that we target is composed of a configurable number of cores, a memory hierarchy consisting of private L1, shared/private L2, and a shared bus interconnect. We consider a benchmark set composed of several parallel shared memory applications. We explore the design space related to the number of cores, L2 cache size, and processor complexity, showing the behavior of the different configurations/applications with respect to performance, energy consumption, and temperature. Design trade-offs are analyzed, stressing the interdependency of the metrics and design factors. In particular, we evaluate several chip floorplans. Their power/thermal characteristics are analyzed, showing the importance of considering thermal effects at the architectural level to achieve the best design choice.

Parallel Multigrid for Anisotropic Elliptic Equations

In this paper two well-known robust multigrid solvers for anisotropic operators on structured grids are compared: alternating-plane smoothers combined with full coarsening and plane smoothers combined with semi-coarsening. The study has taken into account not only numerical properties but also architectural ones, focusing on cache memory exploitation and parallel characteristics. Experimental results for the sequential algorithms have been obtained on two different systems based on the MIPS R10000 processor, but with different L2 cache sizes and memory bandwidths (an SGI O2 workstation and an SGI Origin 2000 system). Although the alternating-plane approach is the best choice for sequential implementations, experimental estimations show poor parallel efficiencies. For the semicoarsening alternative two different parallel implementations have been considered. The first one has optimal parallel characteristics but due to deterioration of the convergence properties its realistic efficiency is not satisfactory. In the second one, some processors remain idle during a short period of time on every multigrid cycle. However, the second parallel algorithm is more efficient since it preserves the numerical properties of the sequential version. Parallel experiments have also been taken on a Cray T3E system.

Utilization of cache area in on-chip multiprocessor

On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on a silicon chip. Utilization of the cache, especially for the remote data is important in the system using such on-chip multiprocessors since the ratio of the off-chip and the on-chip memory access latencies is higher than traditional board-level implementation of the cache coherent non-uniform memory access (CC-NUMA) multiprocessors. We examine two options to utilize the cache resource of the on-chip multiprocessors whose size is restrained by the die area: (1) the instruction and/or private data are only cached at the L1 cache to leave more space on the L2 cache for the shared data; (2) divide cache area into the L2 and the remote victim caches or use all the area for the L2 cache. Results of execution-driven simulations show that the first option improved the performance up to 15%. For the second option, a remote victim cache with 1/8 of the L2 cache size improved three out of four benchmark programs by 4–8%. However, the combination of L2 and victim caches that divide the cache area into two halves of the same size was outperformed by the L2 cache occupying the entire cache area in three out of four benchmark programs.

A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect

This superscalar microprocessor is the first implementation of a 32-bit RISC architecture specification incorporating a single-instruction, multiple-data vector processing engine. Two instructions per cycle plus a branch can be dispatched to two of seven execution units in this microarchitecture designed for high execution performance, high memory bandwidth, and low power for desktop, embedded, and multiprocessing systems. The processor features an enhanced memory subsystem, 128-bit internal data buses for improved bandwidth, and 32-KB eight-way instruction/data caches. The integrated L2 tag and cache controller with a dedicated L2 bus interface supports L2 cache sizes of 512 KB, 1 MB, or 2 MB with two-way set associativity. At 450 MHz, and with a 2-MB L2 cache, this processor is estimated to have a floating-point and integer performance metric of 20 while dissipating only 7 W at 1.8 V. The 10.5 million transistor, 83-mm/sup 2/ die is fabricated in a 1.8-V, 0.20-/spl mu/m CMOS process with six layers of copper interconnect.

The case for SRAM main memory

The growing CPU-memory gap is resulting in increasingly large cache sizes. As cache sizes increase, associativity becomes less of a win. At the same time, since costs of going to DRAM increase, it becomes more valuable to be able to pin critical data in the cache---a problem if a cache is direct-mapped or has a low degree of associativity. Something else which is a problem for caches of low associativity is reducing misses by using a better replacement policy. This paper proposes that L2 cache sizes are now starting to reach the point where it makes more sense to manage them as the main memory of the computer, and relegate the traditional DRAM main memory to the role of a paging device. The paper details advantages of an SRAM main memory, as well as problems that need to be solved, in managing an extra level of virtual to physical translation.