kV SiC MOSFETs Research Articles

Degeneration Mechanism of 30 MeV and 100 MeV Proton Irradiation Effects on 1.2 kV SiC MOSFETs

Degeneration Mechanism of 30 MeV and 100 MeV Proton Irradiation Effects on 1.2 kV SiC MOSFETs

Failure Mechanism Analysis of 1.2 kV SiC MOSFETs Under Low-Temperature Storage, Power Cycling, and Short-Circuit Interactions

Failure Mechanism Analysis of 1.2 kV SiC MOSFETs Under Low-Temperature Storage, Power Cycling, and Short-Circuit Interactions

Study on the Single-Event Burnout Effect Mechanism of SiC MOSFETs Induced by Heavy Ions

As a prominent focus in high-voltage power devices, SiC MOSFETs have broad application prospects in the aerospace field. Due to the unique characteristics of the space radiation environment, the reliability of SiC MOSFETs concerning single-event effects (SEEs) has garnered widespread attention. In this study, we employed accelerator-heavy ion irradiation experiments to study the degradation characteristics for SEEs of 1.2 kV SiC MOSFETs under different bias voltages and temperature conditions. The experimental results indicate that when the drain-source voltage (VDS) exceeds 300 V, the device leakage current increases sharply, and even single-event burnout (SEB) occurs. Furthermore, a negative gate bias (VGS) can make SEB more likely via gate damage and Poole–Frenkel emission (PF), reducing the VDS threshold of the device. The radiation degradation behavior of SiC MOSFETs at different temperatures was compared and analyzed, showing that although high temperatures can increase the safe operating voltage of VDS, they can also cause more severe latent gate damage. Through an in-depth analysis of the experimental data, the physical mechanism by which heavy ion irradiation causes gate leakage in SiC MOSFETs was explored. These research findings provide an essential basis for the reliable design of SiC MOSFETs in aerospace applications.

Investigation of Threshold Voltage Instability and Bipolar Degradation in 3.3 kV Conventional Body Diode and Embedded SBD SiC MOSFET

The 3.3 kV SiC MOSFETs are essential for traction applications, so it is important to investigate the reliability of the recently developed high voltage MOSFETs and power modules as they are believed to be more susceptible to the effects of basal plane dislocations (BPDs). This paper presents measurement results and analysis of bipolar degradation and threshold voltage instability in 3.3 kV SiC MOSFETs having two distinct kinds of integrated diode, conventional body diode and embedded Schottky Barrier Diode (SBD). No bipolar degradation was observed both in MOSFET with conventional body diode and with embedded SBD after accumulated test with 100 hours each of 200%, 400% and 600% rated current stress in the 3rd quadrant of operation. However, the output characteristics show 1% (~0.2 mΩ) and 2% (~0.4 mΩ) increase in on resistance (RDS(on)) and 11% (0.23 V) and 5% (0.1 V) increase in threshold voltage (VTH), respectively, after total bipolar degradation test in the case of the MOSFET with conventional body diode and up to 74 hrs of 600% rated current stress in the case of the MOSFET with embedded SBD at 70°C. A rapid large negative VTH shift was observed in the MOSFETs with embedded SBD after ~ 74 hrs of 600% rated current stress. After accumulated Bias Temperature Instability (BTI) test at 150°C, the VTH value at 25°C has increased by 9.7% (0.14 V) and 14.5% (0.2 V) for the MOSFET with conventional body diode and with embedded SBD, respectively, while RDS(on) increased by 1mΩ at 25°C and by 5mΩ at 150°C, for both types of MOSFETs.

Total Ionizing Dose (TID) Effects on the 1.2 kV SiC MOSFETs under Proton Irradiation

In this paper, the effects of various proton irradiation energies and doses on the electrical characteristics of SiC MOSFETs have been evaluated and characterized using a proton accelerator. The devices under test were designed, fabricated and packaged using 1.2 kV/0.6 µm-tech SiC MOSFET processes. The results demonstrate that the threshold voltage (Vth) of the irradiated devices shifted towards negative values due to the radiation-induced positive oxide trapped charges. Moreover, this negative shift in Vth and positive trapped charges of field limiting ring (FLR) oxide led to an increase in output currents and a reduction in the breakdown voltage values.

1.2 kV SiC MOSFET with Low Specific ON-Resistance and High Immunity to Parasitic Turn-On

With the capability to switch at high speed, there are important concerns about Parasitic Turn-On (PTO) when using SiC MOSFETs in switching applications with fundamental half-bridge configuration [1]. In this work, we present 1200V SiC planar MOSFETs with low specific ON-resistance (Rsp), fast switching characteristics and high immunity to PTO. The PTO immunity is verified by experimental comparison to several commercially available SiC MOSFETs.

Power Cycling Performance of 3.3 kV SiC-MOSFETs and the Impact of the Thermo-Mechanical Stress on Humidity Induced Degradation

Recently, silicon carbide (SiC) power modules of the 3.3 kV voltage class became available and are a promising candidate to replace silicon power modules in traction applications. However, the more than three times higher Young’s Modulus compared to silicon leads to a reduced lifetime under thermo-mechanical stress. This could pose a significant obstacle in their implementation, since traction applications are particularly demanding in their mission profiles with respect to load cycling, but also to environmental conditions. Thus, the thermo-mechanical stress is not just limiting the lifetime itself, but might also promote the humidity induced degradation due to delamination or micro-cracks. In this work, multiple power cycling tests at different temperature swings on 3.3 kV SiC MOSFET chips in a power module were performed, to assess their ruggedness under thermo-mechanical stress. Before or afterwards, these modules were tested under standard HV-H3TRB conditions to verify the interaction between thermo-mechanical and humidity stress on the robustness of the modules.

Body Diode Reliability of 4H-SiC MOSFETs as a Function of Epitaxial Process Parameter

In this paper, the authors continue the experimental evaluation of bipolar degradation for different 1.2 kV SiC MOSFETs. All the devices are stressed by pulsed repetitive forward current through the body diode with current densities varying from 1000 A/cm2 up to 5000A/cm2. The 1.2 kV SiC MOSFETs are split into two major groups based on the differences in epitaxial material (Type A and Type B) that are subjected to the pulsed forward current stress through the body diode. Additionally, there is a third group with Type B epitaxial material, where p+ implantation process at different temperature is applied to evaluate potential impact on bipolar degradation. Devices are electrically characterized on the Keysight B1505A power device analyzer, both before and after stress testing to trace the drift in the electric parameters. Lastly, the drift in parameters observed in some of the devices, are additionally correlated by an electroluminescence (EL) and scanning acoustic tomography (SAT) analysis.

Investigation of BPD Faulting under Extreme Carrier Injection in Room vs High Temperature Implanted 3.3kV SiC MOSFETs

Implantation process for high Al dose p+ contact layers in SiC MOSFETs can generate new basal plane dislocations (BPDs). Such BPD faulting under high carrier injection was investigated in SiC MOSFET layers designed for 3.3kV operation with either room temperature (RT) or high temperature (HT) implantations performed for their high dose p+ contact layer. For excess carrier injection levels of ~1x1018 cm-3 implant induced BPDs faulted from the termination regions of the MOSFETs in the case of RT samples, while the HT samples show no BPD faulting because there were no implant-induced BPDs. However, in the active region of the device no BPDs faulted for both the RT as well as HT samples even at a higher carrier injection of ~1x1019 cm-3. Technology computer-aided design (TCAD) simulations show that the lower doped p-well region below the p+ contact in the active area of the device prevents the minority electron density in the p+ contact layer to below 10x the hole density, which limits BPD faulting even when they are present in that layer as in the case of RT implanted samples.

Comparative Study on High-Temperature Electrical Properties of 1.2 kV SiC MOSFET and JBS-Integrated MOSFET

Comparative Study on High-Temperature Electrical Properties of 1.2 kV SiC MOSFET and JBS-Integrated MOSFET

Design of a 1.2 kV SiC MOSFET with Buried Oxide for Improving Switching Characteristics

The 1.2 kV SiC MOSFET with a buried oxide was verified to be effective in improving switching characteristics. It is crucial to reduce the gate–drain charge (QGD) of devices to minimize switching loss (Etotal). The SiC MOSFET with a split gate and device with a buffered oxide have been proposed by previous studies to reduce the QGD of the devices. However, both devices have a common issue of the concentration of the electric field at the gate oxide. In this paper, we propose the 1.2 kV SiC MOSFET with a buried oxide to reduce the QGD and suppress the electric field crowding effect at the gate oxide. We analyzed the specific on-resistance (Ron,sp), QGD and the maximum electric field at the gate oxide in the off state (Eox,max) according to the width (WBO) and thickness of the buried oxides (TBO). The device with the buried oxide, under optimal conditions, showed lower Eox,max and Etotal without significant increase in Ron,sp in comparison to the device with a conventional structure. These results indicate that the buried oxide can improve the switching characteristics of 1.2 kV SiC MOSFETs.

Ultrafast Optically Controlled Power Switch: A General Design and Demonstration With 3.3 kV SiC MOSFET

Ultrafast Optically Controlled Power Switch: A General Design and Demonstration With 3.3 kV SiC MOSFET

Overvoltage Protection of Series-Connected 10kV SiC MOSFETs Following Switch Failures in MV 3L-NPC Converter for Safe Fault Isolation and Shutdown

Overvoltage Protection of Series-Connected 10kV SiC MOSFETs Following Switch Failures in MV 3L-NPC Converter for Safe Fault Isolation and Shutdown

A 10 kV SiC MOSFET Power Module with Optimized System Interface and Electric Field Distribution

A 10 kV SiC MOSFET Power Module with Optimized System Interface and Electric Field Distribution

Dynamic Voltage Balancing Across Series-Connected 10 kV SiC JBS Diodes in Medium Voltage 3L-NPC Power Converter Having Snubberless Series-Connected 10 kV SiC MOSFETs

Dynamic Voltage Balancing Across Series-Connected 10 kV SiC JBS Diodes in Medium Voltage 3L-NPC Power Converter Having Snubberless Series-Connected 10 kV SiC MOSFETs

A Megawatt-Scale Si/SiC Hybrid Multilevel Inverter for Electric Aircraft Propulsion Applications

This paper presents the design and development of a megawatt-scale medium-voltage (MV) hybrid inverter prototype to validate its feasibility and potentials for the electric propulsion on the next-generation electric aircraft system with an onboard MV dc distribution, e.g., 3 kV dc bus in this work. The proposed hybrid converter consists of a three-level active-neutral-point-clamped (ANPC) stage using 3.3 kV silicon IGBTs cascaded with an H-bridge stage using cost-effective 1.2 kV SiC MOSFETs in each phase. Comprehensive design and evaluation of the full-scale prototype are elaborated, including the low-inductance busbar design, converter architecture optimization and system integration. In addition, a low computational cost space vector modulation with common-mode voltage (CMV) reduction feature is proposed to fully exploit the benefits of SiC MOSFET in this hybrid topology. Extensive simulation and experimental results are provided to demonstrate the performance of each power stage and the full converter assembly in both the steady-state operation and variable frequency operations. Compared with the widely adopted IGBT based ANPC converter in MV applications, the proposed 7-L hybrid inverter system features higher power efficiency, reduced harmonics, higher dc voltage utilization, reduced CMV and lower dv/dt, while remains cost effective compared to the solution using MV SiC MOSFETs.

SiC Three-Level Neutral-Point-Clamped Converter With Clamping Diode Volume Reduction Using Quasi-Two-Level Operation

Medium voltage (MV) SiC MOSFETs have recently garnered considerable attention in the medium-voltage high-power areas like high-frequency solid-state transformers and multilevel converters. While direct series connection of these MOSFETs is an option for higher voltage levels, it requires complex voltage balancing approaches for device voltage balancing during fast switching transients. Alternatively, converter-level solutions such as the three-level (3L) neutral-point-potential (NPC) converter can be used. This paper proposes a new modulation strategy, combining 3L and Quasi-two-level (Q2L) modulations, to minimize the rating and volume of clamping diodes by tightly controlling the thermal stress on the diodes. This approach achieves better efficiency, higher power density, and a simpler converter bus-structure to stack two SiC MOSFETs effectively in series. We present a real-time clamping diode loss estimation to improve the effectiveness of the proposed modulation strategy. To verify the proposed converter-level approach and modulation strategy, we test a 20 kV rated phase-leg with two 10 kV SiC MOSFETs and 3.3 kV SiC diodes.

Humidity Robustness of 3.3kV SiC-MOSFETs for Traction Applications - Compared to Standard Silicon IGBTs in Identical Packages

Silicon carbide (SiC) MOSFETs are gaining more and more market share in typical silicon (Si) IGBT applications such as traction or renewable energies. Especially in reliability sensitive traction applications, medium voltage IGBT-modules (3.3 kV-6.5 kV) are widely used and introducing SiC-MOSFETs to such industries is the next self-evident step already on the way. While their superior electrical performance has been generally accepted already (e.g. [1]), SiC-modules have not yet established a track record of high reliability in this voltage class. For this study, 3.3kV SiC-MOSFET-switches were compared to standard Si-IGBTs regarding their humidity robustness under high voltage bias. Both chip types had been assembled in the same traction rated packages to exclude this influence. The Si-IGBTs resembled the well-known industry standard performance, while the SiC-MOSFETs show no degradation within the reported test time of 2000 h. Given the fact [2], that the latest Si-IGBT generation offers a much better humidity performance as well, the standardised HV-H³TRB is no longer sufficient to provoke failures within a reasonable testing time. On the one hand, this suggests that humidity driven failures will not be an issue under field conditions anymore. On the other hand, even harsher tests are required to investigate differences in humidity performance.

Body Diode of 1.2kV SiC MOSFET: Unipolar and Bipolar Operation

In this work, we investigate the Body Diode (BD) of a 40mOhm, 1.2kV SiC MOSFETs. We performed DC measurements and switching measurements, at Room Temperature (RT) and High Temperature (HT) (T=175°C), together with TCAD simulation and calibration. In switching measurements, we focused on the low side (LS) switch turn-on event, i.e., the BD turn-off event. We demonstrated that unipolar and bipolar BD can both be achieved with different VGS. With VGS=-5V, BD conducts in bipolar mode with carriers being injected via pn junction. This is rather well known in literature and is well characterized by the Negative Temperature Coefficient (NTC) of BD VF. Switching with BD VGS=-5V show strong reverse recovery-temperature dependent that caused by the augmented minority carrier injection at high temperature. Unipolar BD is achieved by channel conduction at VGS=0V and it is well characterized by BD VF - Positive Temperature Coefficient (PTC). Thanks to the unipolar nature, turn-on switching with BD VGS=0V show no reverse recovery-temperature dependent.

Pulsed Forward Bias Body Diode Stress of 1200 v SiC MOSFETs with Individual Mapping of Basal Plane Dislocations

Bipolar degradation is a known problem in the development of SiC MOSFETs when the body diodes (p+ body/ n-drift layer) are forward biased. Mostly higher voltage classes like the 1.7 kV or 3.3 kV SiC MOSFETs have been studied in literature resulting with significant Rdson increase [1-2]. In this work, body diode stress was conducted for 1.2kV SiC MOSFETs, which were mapped with Infra-Red photoluminescence (IR-PL) to determine and localize the exact number of BPDs present in the drift layers of each die [3, 4] and grouped by this criterion. Devices were stressed at extremely high current densities (1200 – 1700 A/cm2) under pulsed conditions. The post-stress analysis shows non-negligible increase of Rdson and Vf. Bipolar degradation occurring from stressing the body diodes at high forward current densities was confirmed by electroluminescence analysis.