Known Good Dies Research Articles

Collective Die Bonding: An Enabling Toolkit for Heterogeneous Integration

The increasing demand for high performance devices with increased functionality onto a single device/package and with reduced form factor were the main factors driving the development of heterogeneous integration technology. Heterogeneous integration (HI) refers to the assembly and packaging of multiple separately manufactured components onto a single chip in order to increase functionality. Components with different functionality, substrate materials and process technologies are joined in a single package in a System in Package (SIP) approach. The functionality of the components could vary throughout the entire device supply chain starting from signal processors to memory, micro-electro-mechanical systems (MEMS) and silicon photonics. The possibility to join multiple functionalities onto a die enables new packaging architectures and design concepts. One such concept is based on the not new concept of die-to-wafer bonding but allows for bonding multiple dies to a wafer in a single process. Such technological approach requires a reliable local multiple-dies bonding technology compliant also to state of the art optical alignment accuracy. Packaging is the final manufacturing process transforming devices into functional products for the end user. Packaging must provide electrical and photonic connections for signal input and output, power input, and voltage control. It also provides for thermal dissipation and the physical protection required for increased product reliability.In this work we report results using a method and process flow enabling local die bonding compatible with the highest alignment accuracy and cleaning requirements to support a very high yield. A customized temporary carrier with alignment features was utilized to place known good dies (KGD) on the carrier and enable die processing prior to the final bonding process. Such carriers with KGD’s (figure 1) were successfully processed using direct bonding, hybrid bonding, adhesive bonding and metal bonding using as bonding partner different substrate materials like silicon and III-V semiconductor. The process success was verified by the final transfer rate, scanning acoustic microscope imaging and TEM cross section analysis (figure 2). In addition other metrology methods have been identified to monitor the process stability. Figure 1

Collective Die Bonding: An Enabling Toolkit for Heterogeneous Integration

The increasing demand for high performance devices with increased functionality onto a single device/package and with reduced form factor were the main factors driving the development of heterogeneous integration technology. Heterogeneous integration (HI) refers to the assembly and packaging of multiple separately manufactured components onto a single chip in order to increase functionality. Components with different functionality, substrate materials, and process technologies are joined in a single package in a System in Package (SIP) approach. The functionality of the components could vary throughout the entire device supply chain starting from signal processors to memory, micro-electro-mechanical systems (MEMS), and silicon photonics. The possibility to join multiple functionalities onto a die enables new packaging architectures and design concepts. One such concept is based on the not new concept of die-to-wafer bonding but allows for bonding multiple dies to a wafer in a single process. Packaging is the final manufacturing process transforming devices into functional products for the end user. Packaging must provide electrical and photonic connections for signal input and output, power input, and voltage control. It also provides for thermal dissipation and the physical protection required for increased product reliability. In this work, we report results using a method and process flow enabling local die bonding compatible with the highest alignment accuracy and cleaning requirements to support a very high yield. A customized temporary carrier with alignment features was utilized to place known good dies (KGD) on the carrier and enable die processing prior to the final bonding process.

Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip

A systematic design methodology is presented for custom Network-on-Chip (NoC) in three-dimensional integrated circuits (3D-ICs). In addition, fault tolerance is supported in the NoC if extra links are included in the NoC topology. In the proposed method, processors and the communication architecture are synthesized simultaneously in the 3D floorplanning process. 3D-IC technology enables ICs to be implemented in smaller size with higher performance; on the flip side, 3D-ICs suffer yield loss due to multiple dies in a 3D stack and lower manufacturing yield of through-silicon vias (TSVs). To alleviate this problem, a known-good-dies (KGD) test can be applied to ensure every die to be packaged into a 3D-IC is fault-free. However, faulty TSVs cannot be tested in the KGD test. In this article, the proposed method deals with the problem by providing fault tolerance in the NoC topology. The efficiency of the proposed method is evaluated using several benchmark circuits, and the experimental results show that the proposed method produces 3D NoCs with comparable performance than previous methods when fault-tolerant features are not realized. With fault tolerance in NoCs, higher yield can be achieved at the cost of performance penalty and elevated power level.

(Invited) Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration

3D chip stacking approaches with TSV (thorough-silicon vias) are mainly classified into three categories: chip-to-chip, wafer-to-wafer, and chip-to-wafer 3D integration. The chip-to-chip technologies are widely used for traditional microelectronic packaging in which KGDs (known good dies) are assembled using one-by-one pick-and-place techniques. Although the assembly yield is high due to the use of KGDs, the assembly throughput is not sufficiently high, compared with wafer-to-wafer approaches. However, wafer-to-wafer technologies have a serious issue in total production yield that is exponentially decreased with the number of stacked layers because the failure dies cannot be removed from the wafers to be stacked. Therefore, chip-to-wafer 3D integration is thought to be a promising candidate to satisfy both the throughput and yield issues. However, chip-to-wafer 3D integration potentially has a trade-off between assembly throughput and alignment accuracies in the conventional robotic pick-and-place techniques. In order to address the problems, we have proposed and developed multichip-to-wafer 3D integration using liquid surface tension. From the technical point of view of chip-to-wafer bonding, we talk about the basic concept and recent studies of the self-assembly based 3D integration. These approaches using surface tension-driven multichip assembly are divided into two methodologies: one is non-transfer stacking without carrier wafers and the other one is transfer stacking with them. These carrier wafers are typically used for temporary wafer bonding in standard 3D integration processes. Here, we also introduce temporary multichip bonding technologies applicable to 3D integration with multichip transfer stacking in which an inorganic temporary adhesive and a debonding layer sensitive to near UV lasers are utilized. In this presentation, we introduce our multichip-to-wafer 3D integration studies with non-transfer and transfer stacking particularly focused on solder microbump bonding (indium/gold and tin/cupper), CVD (chemical vapor deposition)-oxide/CVD-oxide direct bonding, and hybrid bonding through a new material of Cu nano-pillars that have been most recently reported toward upcoming IoT (internet of things) and trillion sensor societies.

Capillary Self-Assembly for 3D Heterogeneous System Integration and Packaging

ABSTRACTThe self-assembly of known good dies (KGDs) on substrates using the liquid capillary method is shown to be a promising technology to achieve three-dimensional (3D) heterogeneous system integration and packaging. Firstly, the effects of the edge structures of self-assembled substrates and chips on alignment accuracies were investigated. When hydrophobic sidewalls with 10-µm-height steps were applied to both chips and assembly sites formed on substrates, the alignment accuracy within 1.0 µm was realized. The alignment accuracies were within 2.0 µm using either substrates or chips having 10-µm-height step structures with hydrophobic sidewalls. Self-assembly of 12-ch vertical-cavity surface-emitting lasers (VCSELs) with a long rectangle shape on glass substrates were also demonstrated. Separation of assembly sites into twelve areas enhanced the resultant force acting on the VCSEL short edge. The enhanced resultant force provided the high alignment accuracies within 2.0 μm. After the self-assembly of the VCSEL and the subsequent thermal compression, the chips successfully exhibited no degradation of their current–voltage (I–V) characteristics and appropriate 850-nm light emission. We demonstrated self-assembly and microbump bonding using non-conductive film (NCF)-covered dies with Cu/Sn microbumps for high-throughput and high-yield multichip-to-wafer 3D integration. The self-assembly of the NCF-covered dies provided high alignment accuracy within 1.1 μm on average. After the self-assembly of NCF-coved dies and thermal compression, microbump chains composed of 7396 bump joints were successfully obtained, resulting in good electrical properties of 32 mΩ/joint without any bridge shorts and failures. The variations of microbump joint resistance were maintained within 5% of the initial value after thermal cycle testing of even 1000 cycles.

Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu–SnAg Microbumps and a Nonconductive Film

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

(Invited) Challenges in 3D Integration

Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H2O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.

Cost evaluation on reuse of generic network service dies in three-dimensional integrated circuits

Reuse of existing designs is one of the most effective means for cost reduction. Three-dimensional (3D) stacking technology makes possible reuse of dies in 3D stack. GNet – a 3D architecture for reusing generic network service dies – is herein proposed to construct a network-on-chip (NoC) by virtue of exploiting reuse of known good dies (KGDs). In GNet, generic network service dies (GNSDs) are KGDs that integrate several networks and can be directly used to bond with other dies in 3D stack. Flexible and configurable design of GNet makes it suitable to requirements in various application circumstances. A comprehensive cost model, which combines the design cost model, reuse model and fabrication model, is introduced to evaluate different architectures from the design phase to the fabrication phase. Experiments show that GNet is more cost efficient than the general 3D implementations.

Multichip Self-Assembly Technology for Advanced Die-to-Wafer 3-D Integration to Precisely Align Known Good Dies in Batch Processing

An advanced die-to-wafer 3-D integration using a surface-tension–driven multichip self-assembly technology was proposed to 3-D stack a large number of known good dies (KGDs) in batch processing. The parallel self-assembly with a unique multichip pick-up tool was newly applied to die-to-wafer 3-D integration to overcome throughput and yield problems in conventional 3-D integration approaches. In addition, novel batch transfer of chips self-assembled on a carrier wafer to the corresponding target wafer was demonstrated. By using the multichip self-assembly, many KGDs can be precisely aligned and temporarily placed on a carrier wafer all at once, and then, the self-assembled KGDs can be simultaneously transferred to another target wafer in a face-to-face bonding manner at the wafer level. Average alignment accuracy was found to be approximately 400 nm when a hundred 3-mm-square chips were self-assembled on carrier wafers with small droplets of an aqueous solution. The alignment accuracy was experimentally proven to be fairly dependent on liquid surface tension as a self-assembly parameter. The liquid wettability contrast between the chip assembly areas and the surrounding areas formed on carrier wafers was another key parameter for alignment accuracy. The former and the latter areas were rendered high hydrophilic and hydrophobic. These areas, respectively, showed water contact angles less than 5 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$^{\circ}$</tex></formula> and 115 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}$</tex></formula> . Therefore, various sizes of chips (3 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 3 mm, 5 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\,\times\,$</tex></formula> 5 mm, 4 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 9 mm, and 10 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 10 mm) were self-assembled on a carrier wafer with high alignment accuracy, and further, the self-assembled chips were successfully transferred to the other faced target wafer in a batch.

A Die-Selection Method Using Search-Space Conditions for Yield Enhancement in 3D Memory

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a highenough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel dieselection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking

AbstractWe have demonstrated that a number of known good dies (KGDs) can be precisely aligned in batch and stacked on LSI wafers by our chip-to-wafer three-dimensional (3D) integration technology using an innovative self-assembly technique. Compared with conventional robotic pick-and-place chip assembly, the fluidic self-assembly can provide high-throughput chip alignment and bonding, and the resulting self-assembled chips have high alignment accuracy of approximately 0.3 micron on average. Immediately after chip release, the chips are aligned onto the predetermined hydrophilic bonding areas in a short time within 0.1 sec by the surface tension of aqueous liquid used in our self-assembly. By using the self-assembly, a number of KGDs with different chip sizes, different materials and different devices can be stacked in high yield to give highly integrated 3D chips we call the 3D Super Chip.

New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration

A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips. By using these key technologies, successful fabrication of 3D LSI test chips with vertical interconnections consisting of In–Au microbumps and buried interconnections filled with polycrystalline silicon (poly-Si) was demonstrated. The test chips was composed of three kinds of very thin chip of 5, 6, and 7 mm2 and ranging in thickness from 30 to 90 µm. Each chip is tightly bonded using a low-viscosity epoxy adhesive as a dielectric material.