Collective Die Bonding: An Enabling Toolkit for Heterogeneous Integration

Abstract

The increasing demand for high performance devices with increased functionality onto a single device/package and with reduced form factor were the main factors driving the development of heterogeneous integration technology. Heterogeneous integration (HI) refers to the assembly and packaging of multiple separately manufactured components onto a single chip in order to increase functionality. Components with different functionality, substrate materials, and process technologies are joined in a single package in a System in Package (SIP) approach. The functionality of the components could vary throughout the entire device supply chain starting from signal processors to memory, micro-electro-mechanical systems (MEMS), and silicon photonics. The possibility to join multiple functionalities onto a die enables new packaging architectures and design concepts. One such concept is based on the not new concept of die-to-wafer bonding but allows for bonding multiple dies to a wafer in a single process. Packaging is the final manufacturing process transforming devices into functional products for the end user. Packaging must provide electrical and photonic connections for signal input and output, power input, and voltage control. It also provides for thermal dissipation and the physical protection required for increased product reliability. In this work, we report results using a method and process flow enabling local die bonding compatible with the highest alignment accuracy and cleaning requirements to support a very high yield. A customized temporary carrier with alignment features was utilized to place known good dies (KGD) on the carrier and enable die processing prior to the final bonding process.