Kinds Of Gates Research Articles

Design and Simulation of Linear All-Optical Comparator Based on Square-Lattice Photonic Crystals

An optical comparator is an important logic circuit used in digital designs. Photonic crystals are among the platforms for implementing different kinds of gates and logic circuits, and they are structures with alternating refractive indices. In this paper, an optical comparator is designed and simulated based on a square lattice photonic crystal. In the design of this comparator, a small-sized structure is used. The simulation results show that in the proposed comparator, there is a high difference between logical values “0” and “1”, which are defined based on the optical power level. Due to the small size of this comparator and the adequate difference between logical values “0” and “1”, this structure suits photonic integrated circuits with high accuracy. The proposed structure footprint is 149.04 µm2, and the calculated rise time for this circuit is less than 0.4 ps.

Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates

The conversion method of netlists consisting of conventional logic gates to RSFQ circuits is proposed. It treats netlists for CMOS circuits as the design entry and converts them to the netlists of RSFQ circuits, considering the reduction of the number of clocked gates, including D flip-flops (DFFs) for path balancing. It utilizes two kinds of special RSFQ gates for the reduction. One is a confluence buffer that can be utilized for realizing logic-or. The other is a small resettable DFF which can be utilized as an NIMPLY gate with the tuning of the order of pulse arrivals. The detection methods of replaceable gates with those two kinds of gates are proposed. An automatic test pattern generation tool is utilized for detecting replaceable or gates to speed up the previously proposed detection method. To minimize the number of clocked gates considering the cost of replacements, the selection problem of gates for replacements with those special RSFQ gates and the assignment of a logic level for each gate are formulated as an instance of integer linear programming. The proposed conversion method has been evaluated with ISCAS85 circuits, a 32-bit ALU, and a 64-bit ALU. The evaluation results show that the number of clocked gates and the latency in the cycles of circuits is reduced by about 10%. The delay time of the converted circuits has been estimated and the reduction of delay overhead is discussed.

Symultaniczność i kompilacja a obraz miejsca

Architektura – jest wydzielaniem przestrzeni, konstruowanym z tworzywa, będącego kompilacją elementów materialnych i niematerialnych. Życie człowieka ma charakter przestrzenny, odbywa się w przestrzeni jego egzystencji: przez niego wytworzonej i zastanej. Człowiek egzystuje w przestrzeni behawioralnej, wśród architektury miasta, która jest swoistym medium – środkiem przekazu informacji składających się sumarycznie na percepcjonowane przez niego treści. Mieszka w przestrzeni realnej i wirtualnej oraz w przestrzeni będącej synergią zbudowaną z obu.Węzeł – to miejsce spotkań: pasaży, ulic… Konstruowany jako miejsce formalnie i funkcjonalnie ważne: do spotkań w mieście. Ma swoje działanie synergiczne. Budowanie węzłów – to budowanie możliwości do powstawania potencjalnych Miejsc Strategicznej Interwencji. To miejsca: kreowania zdarzeń i swoista furtka do różnorakich doznań, percepcji świata materialnego i wirtualnego oraz fantasmagorii – będących konsekwencja ich wzajemnych relacji. Konstruują je: znaczenie w geografi i miasta, znaczenie użytkowe, uformowanie kubaturowe, wydarzenia historyczne i współcześnie przekazywane informacje. Miasto, to co prawda duży dom – ale przy założeniu, że węzeł miejski jest projektowany, a nie powstaje przypadkowo, jego wybudowanie – jako obiektu architektonicznego, zespołu takich obiektów bądź założenia urbanistycznego – nie musi być krótsze niż konstruowanie w nim treści.

Multibands tunneling in AAA-stacked trilayer graphene

We study the electronic transport through np and npn junctions for AAA-stacked trilayer graphene. Two kinds of gates are considered where the first is a single gate and the second is a double gate. After obtaining the solutions for the energy spectrum, we use the transfer matrix method to determine the three transmission probabilities for each individual cone τ=0,±1. We show that the quasiparticles in AAA-stacked trilayer graphene are not only chiral but also labeled by an additional cone index τ. The obtained bands are composed of three Dirac cones that depend on the chirality indexes. We show that there is perfect transmission for normal or near normal incidence, which is a manifestation of the Klein tunneling effect. We analyze also the corresponding total conductance, which is defined as the sum of the conductance channels in each individual cone. Our results are numerically discussed and compared with those obtained for ABA- and ABC-stacked trilayer graphene.

Automatic gate design model from wood & tire for farmers

Indonesia is one of the potential paddy farming area in Southeast Asia, and North Sumatra Province is one of many provinces that provides it. Yet, Indonesia is still importing rice from foreign country, eventhough today the government has been willing to supply its own need. Almost 10% irrigation areas in Indonesia are connected to sea current, which means it must have a system to manage the circulation of fresh water and block the seawater from entering the irrigation area through the irrigation channel. Many systems use gates to control the water management, and most of them are using automatic sluice gate because the gates are usually positioned far from village, this makes the manual operating become difficult. Unfortunately, not all farmers can use this kind of gate due to its accessibility and cost. This research was done to design the automatic gates, which are easy to build, user friendly, low cost and dependable. In the future, poor farmers or farmers who do not have connection to government, can make this gate by themselves. The research was conducted in laboratory, using flume, pumps, reservoir, and gate prototype.

Comparison of the sensitivity to systematic errors between nonadiabatic non-Abelian geometric gates and their dynamical counterparts

We investigate the effects of systematic errors of the control parameters on single-qubit gates based on non-adiabatic non-Abelian geometric holonomies and those relying on purely dynamical evolution. It is explicitly shown that the systematic error in the Rabi frequency of the control fields affects these two kinds of gates in different ways. In the presence of this systematic error, the transformation produced by the non-adiabatic non-Abelian geometric gate is not unitary in the computational space, and the resulting gate infidelity is larger than that with the dynamical method. Our results provide a theoretical basis for choosing a suitable method for implementing elementary quantum gates in physical systems, where the systematic noises are the dominant noise source.

Parameters extraction of hafnium based gate oxide capacitors

From quantum simulations of both capacitance and current measurements, the main physical parameters (dielectric thickness and permittivity, doping levels) of hafnium based (HfSiO x and HfO 2) gate oxide capacitors have been extracted. Three kinds of gates (n +-polysilicon, totally silicided (TOSI) NiSi and metal TiN gates) have been studied. In the case of thick (EOT between 11.1 and 12.3 nm) HfSiO x gate oxides or thin (EOT inferior to 2 nm) HfO 2 stacks with n +-polysilicon or TiN gates, a good agreement between simulations and experimental data is obtained. Electron tunneling currents are prevalent in these stacks except for the specific case of TiN/HfO 2 stacks in p-substrate accumulation mode. In this case, electron and hole tunneling transparencies become of the same order of magnitude. Hole transport contribution can no more be neglected and should be taken into account in simulations.

Delay Time Estimation Model for Large Digital CMOS Circuits

Delay time estimation in simulation or design verification step during a design cycle has become more and more important as the meaning of performance prediction. This paper proposed a delay estimation model for digital CMOS circuits, which works in gate-level but the modeling process includes the characteristics of MOSFETs. This model can handle the variation according to the kind of gates, input transition time, output load(fan-out), and transistor sizes of a gate. The procedure to find the general model was that, a delay model for CMOS inverter was extracted first, then it was extended to other gate by converting it into an equivalent inverter. The resulting model was evaluated and compared with SPICE simulation, which showed that the proposed model has the accuracy of less than 5% relative error rate to the SPICE results for each case and the speed of about 70 times faster than SPICE.