Key Functional Blocks Research Articles

Enterprise resource planning system in the food industry

This article will review enterprise resource planning systems, including the general characteristics and requirements for systems, the possibility of using systems for the food industry, performed a comparative analysis of existing systems based on the current situation on the Russian IT services market, the geopolitical situation and prospects for development in the future. The author provides information based on the dynamics of the development of key functional blocks of enterprise management systems, describes the structure of the most popular solutions, in addition, the possibilities and requirements for systems from the business side. As part of the comparative analysis, the strengths and weaknesses of the available enterprise resource planning systems, such as: 1C:ERP2, SAP, Odoo, Galaxy, Compass and Sail, including description of functional blocks, integration processes, features, availability, security, updating and technical support, user interface usage and most importantly taking into account the specific features of the food industry, a list of goals that should be covered by the capabilities of the system is defined. In parallel with the overview of the general functions and features of the systems, the issues of economic efficiency and economic benefits from the food industry enterprise management system usage are took into account. The author described the main stages of the implementation of these systems, with explanations for each stage, issues of data security, reporting, processes and workflow. In addition to a technical description of processes and technical characteristics, the author will present statistical data on the advantages of enterprise resource planning system usage in the context of economic and production indicators, examples of managerial decision-making based on data received and processed by the system. Based on the key business indicators, both economic and production and logistics, the effectiveness of the use of industrial enterprise management systems in the food industry will be proved.

Energy Efficient Enhancement in a 5.8 GHz Batteryless Node Suitable for Backscattering Communications

This work presents a compact batteryless node architecture suitable with the backscattering communication (BackCom) approach. The key functional blocks are demonstrated at 5.8 GHz, making use of commercially available components involving a DC/DC step-up converter, a 3.3 V data generator, and an ASK backscattering modulator based on a single GaAs HEMT in a cold-FET configuration. The node integrates a patch antenna exhibiting a non-50 Ω optimal port impedance; the value is defined by means of a source pull-based optimization technique aimed at maximizing the DC/DC input current supplied by the RF to DC converter. This approach maximizes the node compactness, as well as the wireless power conversion efficiency. A prototype was optimized for the −5 dBm power level at the input of the RF to DC converter. Under this measurement condition, the experimental results showed a 63% increase in the harvesting current, rising from 145 to 237 μA, compared to an identical configuration that used a microstrip matching network coupled with a typical 50-Ω patch antenna. In terms of harvested power, the achieved improvement was from −13.2 dBm to −10.9 dBm. The conversion efficiency in an operative condition improved from 15% to more than 25%. In this condition, the node is capable of charging a 100 μF to the operative voltage in about 27 s, and operating the backscattering for 360 ms with a backscattering modulation frequency of about 10 MHz.

AMD-Xilinx Kria as a Basis for Industrial Equipment Embedded Control System

This article presents a promising embedded control system designed to implement highly complex algorithms in industrial equipment that requires multi-axis positioning and high-speed data transmission. Brief information about the current trends in the development of the user interface of industrial equipment is given, the relevance of control systems with a graphical interface and support for touch displays is noted. The characteristics of the previously developed control system (based on the Zynq-7000 chip) are given, the shortcomings of this system are noted. The use of the Kria SOM module, developed by AMD-Xilinx (USA), is proposed. The key functional blocks of the control system are indicated, the structure of the embedded software is briefly shown. A comparison of two variants of the system — based on Zynq-7000 and Kria SOM — is made. The conclusion about the advantages of using the Kria SOM module (namely: the increase in the speed of mathematical calculations up to 5 times — depending on the task, decrease in the cost of components up to 10 times, simplification of the design of a printed circuit board by reducing the number of layers from 14—16 to 10, significant reduction in time cost of developing a circuit diagram and printed circuit board) is made. The advantages of the Kria SOM as the basis for building a control system with artificial intelligence capabilities are noted.

Compact chip-scale guided cold atom gyrometers for inertial navigation: Enabling technologies and design study

This work reviews the topic of rotation sensing with compact cold atom interferometers. A representative set of compact free-falling cold atom gyroscopes is considered because, in different respects, they establish a rotation-measurement reference for cold guided-atom technologies. This review first discusses enabling technologies relevant to a set of key functional building blocks of an atom chip-based compact inertial sensor with cold guided atoms. These functionalities concern the accurate and reproducible positioning of atoms to initiate a measurement cycle, the coherent momentum transfer to the atom wave packets, the suppression of propagation-induced decoherence due to potential roughness, on-chip detection, and vacuum dynamics because of its impact on sensor stability, which is due to the measurement dead time. Based on the existing enabling technologies, the design of an atom chip gyroscope with guided atoms is formalized using a design case that treats design elements such as guiding, fabrication, scale factor, rotation-rate sensitivity, spectral response, important noise sources, and sensor stability.

Approach to the organization of decision support in the formulation of innovative regional development strategies based on adaptive-simulation model

This article deals with the formulation of a decision support system (DSS) in the field of regional development management. The review of existing approaches in this area presented here attests, on the one hand, to their diversity, and on the other hand allows us to draw conclusions about the need to address several methodological and practical issues of decision support in terms of innovative development of regions. Based on this, the goal of the research was to develop the concept of DSS to justify the parameters of an innovative development strategy for regional development based on adaptive mechanisms for coordinating the interests of economic agents. The methodology of the study is based on the synthesis of various approaches in the framework of integration into the structure of adaptive simulation models of problem-oriented knowledge bases with the mechanism of logical inference, as well as intelligent technologies for processing semi-structured information used to find solutions in the process of shaping and adjusting the parameters for managing innovative development of a region. The result of the study is a theoretical justification for developing problem-oriented DSS, including a description of the interrelated stages that determine the main design features of this tool. In the framework of the study, a conceptual scheme for implementing DSS in the field of managing innovative development of regions is proposed, and the key functional blocks of the proposed tools are described. In addition, the place of existing tools in the structure of the regional development management system is determined, and we show the possibilities of their use in the formation of forecast-planned assessments of the development of the region, as well as in the evaluation of the effectiveness of alternative management actions. The proposed tools will expand the possibilities of applying the methods of management theory and decision support, intelligent information technology, economic and mathematical methods and modern computer simulation technologies for strategic planning of socio-economic systems of macro- and meso-level. In practice, the tools may be of interest to public authorities in solving problems in in the formulation of innovative regional development strategies for Russian regions, the formation of medium-term forecasts and the justification of the parameters of social, economic and budgetary policy.

Broadband 240-GHz Radar for Non-Destructive Testing of Composite Materials

A broadband frequency-modulated continuous-wave radar that operates at a center frequency of 240 GHz is being presented. The main focus of this paper is on the monolithic integration of the millimeter wave transceiver front end circuit and its validation at the wafer level, module level, and system level. The transceiver front end chip was developed using a 35-nm InAlAs/InGaAs-based metamorphic high electron mobility transistor technology with an advanced back-end-of-line (BEOL) process. The key functional building blocks were developed as part of a broadband integrated circuit library for millimeter wave, and THz phased array applications. The transmit path (TX) of the transceiver has a 3-dB defined bandwidth of 60 GHz, and output power of 8 dBm was measured at the chip level and 6 dBm at the waveguide module level, respectively. The receive path (RX) exhibited a conversion gain of 10 dB and an average noise figure (NF) of 7 dB, which were measured over a 3-dB defined bandwidth of 40 GHz, or a 10-dB defined bandwidth of 60 GHz. The flatness of the TX and RX was 1 dB for the transmit power and NF between 220 and 260 GHz. The radar was evaluated for its application in nondestructive tomographic imaging of multilayer glass fiber-reinforced materials. A focusing scanning system was used to determine the characteristic features of material samples at different bandwidths up to 65 GHz.

A Building Block IC for Designing Emerging Hybrid and Multilevel Converters

This paper introduces a practical power management integrated circuit (IC) building block, i.e., IC module, which enables the implementation of various emerging hybrid and multilevel power converter topologies in low-power high-frequency applications, operating at switching frequencies up to 10 MHz. Compared to conventional buck- and boost-based topologies, the emerging multilevel and hybrid converters offer significant volume reduction and power processing efficiency improvements. These key factors are significant contributions for modern portable and/or small footprint electronics devices, where size is of great concern. The IC building block (ICBB) consists of two segmented half bridges as well as all the elements needed for implementing mixed-signal current programmed mode (CPM) control. Mixed-signal CPM compatibility coupled with a segmented power stage not only provide inherent current protection and simple controller implementation but also allows for dynamic efficiency optimization. Operation at high-switching frequencies and simple modular design with ICBB are enabled through the development of novel architectures for key functional blocks of the ICBB and a cost-effective solution for level shifting, providing communication between external control signals and module inputs. For example, solutions for high-frequency low-power current sensing and fast digital-to-analog conversion are introduced as well as a capacitive coupling and coding schemes for data transfer. Several identical custom-designed ICBB modules are fabricated in the 0.13- $\mu \text{m}$ CMOS process, each providing up to 2 W of output power, while operating at a switching frequency of up to 10 MHz. The versatility and proper functionality of these modules are verified through simulation and experimental results.

Real-Time Adaptively Regularized Compressive Sensing in Cognitive Radio Networks

Wideband spectrum sensing is regarded as one of the key functional blocks in cognitive radio systems, where compressive sensing (CS) has become one of the promising techniques to deal with the Nyquist sampling rate bottleneck. Theoretical analyses and simulations have shown that CS could achieve both high detection and low false alarm probabilities in wideband spectrum sensing. However, the implementation of CS over real-world signals and real-time processing poses significant challenges due to the high computational burden and reconstruction errors against noise. In this paper, we propose an efficient adaptively regularized iterative reweighted least squares (AR-IRLS) algorithm to implement the real-time signal recovery in CS-based wideband spectrum sensing. The proposed AR-IRLS algorithm moves the estimated solutions along an exponential-linear path by regularizing weights with a series of nonincreasing penalty terms, which significantly speeds up the convergence of reconstruction and provides a high fidelity guarantee to cope with spectral signals with varying bandwidths and power levels. Furthermore, a descent-based decision threshold setting algorithm is proposed to distinguish the primary signals from the mixture of the reconstruction errors and unknown noises. The proposed scheme demonstrates robustness against different sparsity levels at low compressive ratios without degradation of the reconstruction performance. It is tested with the real-world signals over the TV white space after being validated with the simulated signals. Both the simulation and real-time experiments show that the proposed scheme outperforms the conventional iterative reweighted least squares algorithms in terms of convergence speed, reconstruction accuracy, and compressive ratio.

Comparative Performance Evaluation of TCP with Identical and Cross-Variant Congestion Control

The Transmission Control Protocol (TCP), a key functional building block of the Internet, operates as a rate-adaptive end-to-end protocol at the Transport Layer of the network protocol stack. It regulates the prevailing load conditions within the network by getting the source node to adapt the packet transfer rate in accord with the processing capacity of the receiver. The regulation is enforced by means of dropping of packets on the part of the receiver. The TCP sender then reduces the packet injection rate so as to allow the network to recover from congestion. The focus of this paper is performance evaluation of certain notable TCP congestion avoidance algorithms, namely, Vegas, Reno and New Reno. Specifically, a number of performance measures have been analysed based on ns-2 simulation data where the scenarios involved TCP flows operating with identical and cross-variant congestion control mechanisms. Congestion window behaviour, packet loss, throughput, transmission delay and jitter are the performance criteria studied with the setup mentioned. In the flows with identical variants, Vegas outperforms other TCP variants. However, TCP Vegas has been observed to contribute to unfair appropriation of the resources in the cross-variant setting.

GPU-Accelerated Real-Time Path Planning and the Predictable Execution Model

Path planning is one of the key functional blocks for autonomous vehicles constantly updating their route in real-time. Heterogeneous many-cores are appealing candidates for its execution, but the high degree of resource sharing results in very unpredictable timing behavior. The predictable execution model (PREM) has the potential to enable the deployment of real-time applications on top of commercial off-the-shelf (COTS) heterogeneous systems by separating compute and memory operations, and scheduling the latter in an interference-free manner. This paper studies PREM applied to a state-of-the-art path planner running on a NVIDIA Tegra X1, providing insight on memory sharing and its impact on performance and predictability. The results show that PREM reduces the execution time variance to near-zero, providing a 3× decrease in the worst case execution time.

QoS Provisioning in Converged Satellite and Terrestrial Networks: A Survey of the State-of-the-Art

It has been widely acknowledged that future networks will need to provide significantly more capacity than current ones in order to deal with the increasing traffic demands of the users. Particularly in regions where optical fibers are unlikely to be deployed due to economical constraints, this is a major challenge. One option to address this issue is to complement existing narrow-band terrestrial networks with additional satellite connections. Satellites cover huge areas, and recent developments have considerably increased the available capacity while decreasing the cost. However, geostationary satellite links have significantly different link characteristics than most terrestrial links, mainly due to the higher signal propagation time, which often renders them not suitable for delay intolerant traffic. This paper surveys the current state-of-the-art of satellite and terrestrial network convergence. We mainly focus on scenarios in which satellite networks complement existing terrestrial infrastructures, i.e., parallel satellite and terrestrial links exist, in order to provide high bandwidth connections while ideally achieving a similar end user quality-of-experience as in high bandwidth terrestrial networks. Thus, we identify the technical challenges associated with the convergence of satellite and terrestrial networks and analyze the related work. Based on this, we identify four key functional building blocks, which are essential to distribute traffic optimally between the terrestrial and the satellite networks. These are the traffic requirement identification function, the link characteristics identification function, as well as the traffic engineering function and the execution function. Afterwards, we survey current network architectures with respect to these key functional building blocks and perform a gap analysis, which shows that all analyzed network architectures require adaptations to effectively support converged satellite and terrestrial networks. Hence, we conclude by formulating several open research questions with respect to satellite and terrestrial network convergence.

Amplitude spectrum distance: measuring the global shape divergence of protein fragments.

BackgroundIn structural bioinformatics, there is an increasing interest in identifying and understanding the evolution of local protein structures regarded as key structural or functional protein building blocks. A central need is then to compare these, possibly short, fragments by measuring efficiently and accurately their (dis)similarity. Progress towards this goal has given rise to scores enabling to assess the strong similarity of fragments. Yet, there is still a lack of more progressive scores, with meaningful intermediate values, for the comparison, retrieval or clustering of distantly related fragments.ResultsWe introduce here the Amplitude Spectrum Distance (ASD), a novel way of comparing protein fragments based on the discrete Fourier transform of their C α distance matrix. Defined as the distance between their amplitude spectra, ASD can be computed efficiently and provides a parameter-free measure of the global shape dissimilarity of two fragments. ASD inherits from nice theoretical properties, making it tolerant to shifts, insertions, deletions, circular permutations or sequence reversals while satisfying the triangle inequality. The practical interest of ASD with respect to RMSD, RMSDd, BC and TM scores is illustrated through zinc finger retrieval experiments and concrete structure examples. The benefits of ASD are also illustrated by two additional clustering experiments: domain linkers fragments and complementarity-determining regions of antibodies.ConclusionsTaking advantage of the Fourier transform to compare fragments at a global shape level, ASD is an objective and progressive measure taking into account the whole fragments. Its practical computation time and its properties make ASD particularly relevant for applications requiring meaningful measures on distantly related protein fragments, such as similar fragments retrieval asking for high recalls as shown in the experiments, or for any application taking also advantage of triangle inequality, such as fragments clustering.ASD program and source code are freely available at: http://www.irisa.fr/dyliss/public/ASD/.Electronic supplementary materialThe online version of this article (doi:10.1186/s12859-015-0693-y) contains supplementary material, which is available to authorized users.

(Invited) Design and Development of an Organic Operational Amplifier for Use in Low-Cost Smart Sensor Systems

Over the past decade, Organic Electronics has continued to evolve steadily, particularly in the development of simple digital circuits [1]. Efforts have also begun in the development of analog counterpart, for use as key functional blocks in flexible low-cost smart sensor systems [2 - 4]. This however has been generally challenging due to the complexity of the fabrication processes [5], owing to the circuit architecture adapted. In addition, the gain and bandwidth of the amplifier are low, attributed to the low charge carrier mobility of the active layer. Moreover, for solution-processed layers, the possible variability of the parameters can hinder the overall circuit performance [6 - 11]. In this talk, we propose novel approaches in the design of an organic analog circuit such as the Operational amplifier (Op-amp), for integration in a smart sensor technology. We propose methods to tackle and investigate the various issues addressed above. In order to maintain simpler processes, the design of the organic Op-amp adapts a pseudo-PMOS configuration with saturated loads, rather than the alternative CMOS. With such a configuration, only p-channel organic thin-film transistors (OTFTs) are utilised of higher charge carrier mobility, and subsequently require one type of metal contact for the source/drain of the load and driver OTFTs. And with saturated loads, smaller number of input gates is needed compared to the CMOS design [12] for better control of the threshold voltages of the load and driver OTFTs. There are however performance trade-offs to be considered when adapting the pseudo-PMOS designs, particularly in the voltage range for the logic levels, switching point and operational speeds. Nonetheless, such trade-offs can be compensated by adjusted the aspect ratios of the load to driver OTFTs, and utilising additional circuitry so as to boost the gain and attain adequate bandwidth for sensor applications. The Op-amp circuit designs are simulated using appropriate organic parameter values to reflect the conductance and capacitances of the OTFT, including low mobility of the charge carriers and high contact resistances. These models are verified using experimental data of 6,13-bis(tri-isopropylsilylethynyl) pentacene (TIPS) OTFT [13]. The effect of the variability of the parameters such mobility and threshold voltage, on the overall circuit performance are presented, and finally the functionality of the organic Op-Amp in sensing applications is demonstrated.

Design of an Ultra-Low Power CT ΣΔ A/D Modulator in 65 nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation

Abstract A high performance, ultra-low power, fully differential 2nd-order continuous-time ΣΔ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182 nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65 nm CMOS technology is employed to implement the ΣΔ modulator. The modulator achieves a simulated SNR of 53.8 dB over a 400Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45 × 0.50mm2

Why noise is useful in functional and neural mechanisms of interval timing?

BackgroundThe ability to estimate durations in the seconds-to-minutes range - interval timing - is essential for survival, adaptation and its impairment leads to severe cognitive and/or motor dysfunctions. The response rate near a memorized duration has a Gaussian shape centered on the to-be-timed interval (criterion time). The width of the Gaussian-like distribution of responses increases linearly with the criterion time, i.e., interval timing obeys the scalar property.ResultsWe presented analytical and numerical results based on the striatal beat frequency (SBF) model showing that parameter variability (noise) mimics behavioral data. A key functional block of the SBF model is the set of oscillators that provide the time base for the entire timing network. The implementation of the oscillators block as simplified phase (cosine) oscillators has the additional advantage that is analytically tractable. We also checked numerically that the scalar property emerges in the presence of memory variability by using biophysically realistic Morris-Lecar oscillators. First, we predicted analytically and tested numerically that in a noise-free SBF model the output function could be approximated by a Gaussian. However, in a noise-free SBF model the width of the Gaussian envelope is independent of the criterion time, which violates the scalar property. We showed analytically and verified numerically that small fluctuations of the memorized criterion time leads to scalar property of interval timing.ConclusionsNoise is ubiquitous in the form of small fluctuations of intrinsic frequencies of the neural oscillators, the errors in recording/retrieving stored information related to criterion time, fluctuation in neurotransmitters’ concentration, etc. Our model suggests that the biological noise plays an essential functional role in the SBF interval timing.

SeDAX: A Scalable, Resilient, and Secure Platform for Smart Grid Communications

Smart Grid applications are imposing challenging requirements of security and reliability on the N-way communication infrastructure being designed to support multiple grid applications. These challenges stem from the increasing incorporation of distributed renewable energy sources on to the grid, the rising deployment of electric vehicles, and active consumer participation into power grid operations, all of which communicate with the utility control center with varying degrees of priority and security. To address these challenging requirements, we propose SeDAX, a SEcure Data-centric Application eXtensible platform for Smart Grid applications. SeDAX implements scalable, resilient and secure data delivery and data sharing in a wide area network. The platform can scalably handle high volumes of data generated by both applications and sensors. The SeDAX architecture has as its basis a Delaunay Triangulation (DT) network. The properties of the DT graph are leveraged to scalably support secure data-centric (or information-centric) group communication. The primary goals of this platform are to support communication resilience and data availability. The key functional blocks of the SeDAX platform are: (1) a geographic hash forwarding algorithm that operates over the DT graph (DT-GHF), and (2) a DT-based data replication scheme. The forwarding and replication schemes are scalable and cost effective in terms of communication overhead and memory. We describe the design details of the SeDAX platform and present empirical results on the performance of SeDAX as compared with other geometric-based alternatives such as Geographic Hash Table (GHT) forwarding and Content Addressable Networking (CAN). The operation of SeDAX is illustrated in the context of implementing demand response, a known Smart Grid application.

Chemiluminescence Immunoassay Analyzer Control System Based on S3C2410A

Chemiluminescence immunoassay (CLIA) is the combination of chemiluminescence system and immunoassay. CLIA is established as one of the best alternatives to conventional radioimmunoassay for the quantitation of low concentrations of analytes in complex samples. A high-performance CLIA control system based on the embedded microprocessor S3C2410A is presented in this paper. The system principle, the overall structure of the system, the control structure of the key functional blocks and the flow chart of the software are given. The hardware drivers and the application software are developed on the basis of S3C2410A. The experimental results show that the presented system is feasible in the clinical diagnosis and can be used in the automatic chemiluminescence immunoassay analyzer.

Vertical handover (VHO) framework for future collaborative wireless networks

SUMMARYThe paper focuses on the concept of the vertical handover (VHO) among collaborative wireless networks, which is the necessary driver for seamless mobility and thus for the ability of the user to be always best connected. The paper discusses the required enabling architecture for distributed VHO decision making that is based on the principles of the IEEE 1900.4 standard and on the key media‐independent signaling procedure related to the IEEE 802.21 standard. The proposed framework combines the ‘lower‐layer’ and ‘higher layer’ intelligence in a unified and media‐independent way, to drive handover decisions based on rich terminal and network context information. The paper provides a detailed description of the VHO framework and of the key interactions between its key functional blocks. Additionally, the paper includes a series of validation results corresponding to an implementation of the presented framework. Furthermore, the paper includes a discussion comparing the capabilities offered by the proposed framework with those proposed by other similar proposals, which shows the potential benefits and tradeoffs of the introduced concepts. Copyright © 2011 John Wiley & Sons, Ltd.

Phase Compensation Techniques for Low-Power Operational Amplifiers

An operational amplifier is one of the key functional blocks and is widely used in analog and mixed-signal circuits. For low-power consumption, many techniques such as class AB and slew-rate enhancement have been proposed. Although phase compensation is related to power consumption, it has not been clearly discussed from the viewpoint of the power consumption. In this paper, the conventional and the improved Miller compensations and the phase compensation by introducing a new zero are dicussed for low-power operational amplifiers.

An Ultrawideband System Architecture for Tag Based Wireless Sensor Networks

With the latest improvements in device size, power consumption, and communications, sensor networks are becoming increasingly more popular. There has also been a great increase in the popularity of commercial applications based on ultrawideband (UWB). Impulse radio (IR) based UWB technology utilizes noise-like signal, has potentially low complexity and low cost, is resistant to severe multipath, and has very good time domain resolution allowing for location and tracking applications. In this paper, the architecture and performance of a noncoherent low complexity UWB impulse radio based transceiver designed for low data rate, low cost sensor network applications is presented. The UWB-IR transmitter is based on a delay locked loop (DLL) and UWB monocycle pulse generator. The UWB-IR receiver utilises a noncoherent, energy detection based approach, which makes it largely independent of the shape of the transmit waveform and robust to multipath channels. The test circuits are designed for 0.35 /spl mu/m SiGe BiCMOS technology. This paper presents system simulations results as well as the performance of key functional blocks of the designed UWB application specific integrated circuit (ASIC) transceiver architecture. The simulated power consumption of UWB-IR transceiver circuits is 136 mW with 100% duty cycle with a 3.3 V power supply.