Keeper Size Research Articles

Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design

Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.

Design Optimization of FinFET Domino Logic Considering the Width Quantization Property

Design optimization of FinFET domino logic is particularly challenging due to the unique width quantization property of FinFET devices. Since the keeper device in domino logic is sized based on the leakage current of the pull-down network (PDN) (to meet the noise margin constraint), a reliable statistical framework is required to accurately estimate the domino gate leakage current. Considering the width quantization property, this paper presents such a statistical framework, which provides a reliable design window for keeper sizing to meet the noise margin constraint (for the practical range of threshold voltage variation in sub-32-nm technology nodes). On the other hand, the width quantization property restricts the design optimization (including power/performance characteristics) typically achieved via continuous keeper sizing in planar-CMOS domino logic designs. To cope with this restriction, this paper also introduces a novel methodology for FinFET-based keeper design, which exploits the exclusive property of FinFET devices (capacitive coupling between the front gate and the back gate in a four-terminal FinFET) to simultaneously achieve higher performance and lower power consumption. Using this new methodology, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the PDN, but gradually becomes stronger to provide a higher noise margin.

Domino logic with variable threshold voltage keeper

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino (SD) logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a SD circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a SD circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a SD circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced.

Magnetic-Field Design Considerations for a Plated-Wire Memory

Permeable keepers are used in a plated-wire memory to reduce the adjacent bit interference and the current requirement. Computations of a magnetic field have been performed to determine the quantitative effect of the keeper size on the field enhancement in the region where the information is to be stored and on the field reduction outside this region. The field enhancement can be interpreted as the reduction in current for a given magnetic field, and the reduction of the fringing field as the reduction in adjacent bit interference. The numerical results which represent valuable design considerations for a plated-wire memory are presented in graphical form.