Keep-out Zones Research Articles

Spatial Optimization for Energy Island Location and Cable Routing Considering Offshore Zoning

The energy hub concept presents a compelling opportunity to channel electricity from offshore wind farms to the grid, facilitating cross-border energy trading and conversion. However, one of the main challenges lies in the strategic identification of a suitable energy island location and the establishment of an interconnected cable routing path. Part of the complexity arises from the need to navigate offshore zoning regulations and accommodate various spatial uses within the offshore area. This paper exhibits a case study to explore the spatial optimization for a potential offshore energy hub in the North Sea. It aims at finding out an optimal spatial configuration of the offshore energy hub, such that the island location and the associated cable routing do not infringe upon keep-out zones while strategically positioning the hub closer to high-capacity wind farms. To achieve this goal, detailed geographical data incorporating offshore zoning information is leveraged for spatial optimization. The Dijkstra’s algorithm is then applied to identify the optimal island location and cable routing path. The effectiveness of this spatial optimization methodology is demonstrated through a case study involving offshore wind farm sites in the North Sea. Given the real geographical data, simulation results underscore the efficacy of the Dijkstra’s algorithm in determining the optimal energy hub layout. In particular, an optimal spatial design is achieved, based on cable lengths, asset capacities, offshore zoning and island/platform location for a potential offshore energy hub in the North Sea while ensuring compliance with keep-out zoning regulations.

Overtaking collision avoidance for small autonomous uncrewed aircraft using geometric keep-out zones

Autonomous uncrewed aircraft will require collision avoidance systems (CASs) designed with autonomy in mind as they integrate into the increasingly crowded national airspace system. Current uncrewed aircraft CASs typically require a remote pilot to execute avoidance or to provide poorly defined guidance that does not benefit autonomous systems. The Path Recovery Automated Collision Avoidance System (PRACAS) re-plans flight paths to autonomously adjust for collisions using path planners and keep-out zones (KOZs), but it does not currently detect or mitigate overtaking collisions. This work investigates the effect of geometric KOZs on overtaking scenarios for autonomous uncrewed aircraft. KOZ shapes were developed by relating relative velocities and turn rates of aircraft in overtaking scenarios and were tested using PRACAS. The operational ranges for approach heading, relative velocity, and look-ahead time were then determined. The set of KOZs that were developed prevented intruder aircraft from entering the minimum separation distance of one wingspan from the mission aircraft in overtaking scenarios with look-ahead times between 5 and 12 s, relative velocities of 2–20, and approach angles between 110° and −110° measured from the heading of the main UAS. Minimum separation was maintained for low-speed encounters with relative velocities between 1.1 and 2.0 for look-ahead times between 2 and 8 s for all approach angles. With look-ahead times ranging from 5 to 8 s, overtaking collisions of all tested approach angles and relative speeds are handled with more than twice the separation required for success, showing that the KOZs developed are feasible in possible autonomous CASs.

Fabrication and Electrical Characterization of High Aspect Ratio Through-Silicon Vias with Polyimide Liner for 3D Integration.

High aspect ratio (HAR) through-silicon vias (TSVs) are in urgent need to achieve smaller keep-out zones (KOZs) and higher integration density for the miniaturization of high-performance three-dimensional (3D) integration of integrated circuits (IC), micro-electro-mechanical systems (MEMS), and other devices. In this study, HAR TSVs with a diameter of 11 μm and an aspect ratio of 10:1 are successfully fabricated in a low-cost process flow. Conformal polyimide (PI) liners are deposited using a vacuum-assisted spin coating technique, and the effects of spin coating time and speed on the deposition results are discussed. Then, continuous Cu seed layers are fabricated by sequential sputtering and ultrasound-assisted electroless plating. Additionally, void-free and seamless Cu conductors are formed by electroplating. Moreover, a semi-additive method is used to fabricate the redistribution layers (RDLs) on the insulating layers of photosensitive PI (PSPI). Notably, a plasma bombardment process is introduced to remove residual PSPI in the contact windows between RDLs and central pillars. Results show that the resistance of a single TSV from a daisy chain of 144 TSVs with density of 2000/mm2 is about 28 mΩ. Additionally, the S-parameters of a single TSV are obtained using L-2L de-embedding technology, and the experimental and simulated results agree well. The proposed low-cost fabrication technologies and the related electrical characterization of PI-TSVs are significant for the application of HAR TSVs in modern heterogeneous integration systems.

Single-axis attitude control for slew maneuvers with the keep-out zones

The problem of large angle slew maneuvers under the attitude restrictions is considered. The modification of the single axis Lyapunov feedback attitude control is proposed. It “locally” changes the standard attitude controller to accommodate the attitude restrictions avoidance. The problem of the unwanted equilibria appearance is thoroughly investigated. Different keep-out zones intersection cases are considered.

Model Predictive Control to Autonomously Approach a Failed Spacecraft

In this study, a model predictive control (MPC) method is developed for a servicer spacecraft autonomously approaching a tumbling failed spacecraft at an ultraclose range. Flight safety and collision avoidance are basic requirements during the approach. Two types of a failed spacecraft with complex configurations are considered, and a double-ellipsoid composite envelope strategy is designed to model their keep-out zones. Given the keep-out zone of the servicer, two expanded ellipsoids are subsequently introduced to determine the collision and sufficient conditions for collision avoidance are derived by using the form of concave constraint. The tumbling motion of the target is considered, and a CW-based translational dynamics and derived attitude dynamics of the target are formulated to predict the motion of the docking point and keep-out zone. The MPC is formulated to drive the servicer tracking the docking point with collision avoidance and handle constraints including control input saturation and relative velocity bound. Convexification of the collision avoidance constraint and sequential convex programming are adopted for the implementation of MPC. Scenarios on the servicer with different initial positions approaching the target with different angular velocities are simulated, and the simulation results indicate that the proposed MPC method is effective.

Experimental characterisation of coaxial TSV transistor keep out zones

Three-dimensional (3D) integration is an emerging technology that aims to achieve efficient packaging of the multifunctional silicon (Si) die within a single chip package. This system in package approach achieves connectivity between the individual Si die using through Si via (TSV) technology. Coaxial TSVs have emerged as the preferred 3D interconnect for high-frequency packaging applications due to their superior high-frequency electrical characteristics. The interconnect utilises a copper shield to prevent noise and unwanted signal coupling to occur within the Si substrate. However, a potential disadvantage of 3D integration is the large transistor keep-out-zones (KOZs) required to prevent transistor variability caused by thermally induced stress due to the copper-based TSVs in the Si substrate. Currently, only analytical models exist that predict KOZs for various coaxial TSV configurations and determining the precise KOZ is critical to minimise interconnect footprint that results in increased costs due to reductions in Si die area for integrated circuit designers. For the first time, the work has characterised the thermomechanical behaviour of fabricated coaxial TSVs utilising the microRaman spectroscopy technique to define transistor KOZ for both analogue and digital circuital applications.

Rendezvous in Lunar Near Rectilinear Halo Orbits

Near Rectilinear Halo Orbits (NRHO) have been recently identified as suitable location for a cislunar space station, to orbit in the Earth–Moon vicinity and offer long-term infrastructural services to manned and unmanned missions to the Moon and further. Indeed, to reliably perform rendezvous and docking/undocking phases between space vehicles orbiting on highly non-Keplerian orbits, such as NRHOs, represents a fundamental key technology. Rendezvous is well-known for Earth-centred missions, while no mission ever performed it on non-Keplerian orbits. The paper critically discusses the adopted approach and the obtained results in modelling the non-Keplerian relative dynamics and in synthesizing the guidance, to safely rendezvous and dock on NRHOs. The entire study is strongly driven by engineering constraints and mission requirements which lead the practical implementation. The dynamics intrinsic non-linearity—which makes the trajectories highly sensitive to small deviations—is here exploited to benefit both rendezvous operations and safety. The paper shows the relative trajectories, designed in a way that both NRHO central and unstable manifolds are used: the former to ensure the chaser relative orbit to be periodic with respect to the target, the latter to answer the passive safety philosophy here preferred. In fact, chaser deviation from target is naturally obtained, whenever on an unstable direction. Along the approaching trajectory, two holding points are assumed: on the central manifold the farthest, at about 100 km from the target, to prepare for the final approach; if a no-go is commanded, the spacecraft hovers on the central manifold, waiting for the next approach opportunity. The closest holding point is designed to lay on the unstable manifold direction, to privilege risk mitigation through passive safety, since if no active control occurs, the chaser—now just meters away from the target—naturally drifts away. The relative trajectory and approach strategy design, driven by the guidance and mission operations definition in nominal and non-nominal scenarios, is discussed in the paper: the simulations and the analyses that led to the approach corridor shape, keep-out zones radius and collision avoidance manoeuvres settling are here reported. The practical case of the cislunar space gateway servicing is here exploited to present the proposed rendezvous and approach techniques for non-Keplerian scenarios and to highlight the GRANO software tool—developed by the authors at Politecnico di Milano, ASTRA Team—flexibility for general application in the n-body framework.

Numerical investigation on the effect of condensate layer formation around large-size components during vapour phase soldering

The reflow soldering process of large size components was always problematic in microelectronics manufacturing due to the possibility of component displacement failures after soldering; like tombstone formation or skewing, which can be traced back to the different heating of the opposite component sides. During vapour phase soldering, the efficiency of heat transfer highly depends on the thickness of the condensate layer. In this paper, the inhomogeneity of condensate layer formation and its effects were investigated at large size components during vapour phase soldering by numerical simulations. For this purpose, a 3D computational fluid dynamic model was established. According to the condensate layer formation in different cases, the onset differences in the melting of the solder alloy at the opposite leads of the component were calculated. By the results, the risk of the component displacement during reflow soldering was analysed. It was found, that the congestion of the condensate layer around the large size components can cause considerable differences in the onset of the solder alloy melting, which can yield in component displacement failures after soldering. The extent of difference in the onset of melting depends on the location of the component on the board and on the applied soak temperature. Keep-out zones on the board were suggested to reduce the possibility of the component displacement failures during the vapour phase soldering process.

Integration of MEMS in Fan-Out Wafer-Level Packaging Technology based System-in-Package (WLSiP)

The Internet of Things/ Everything (IoT/E) will require billions of single or multiple MEMS/Sensors integrated in modules together with other functional building blocks like processor, memory, connectivity, built-in security, power management, energy harvesting, and battery charging. The success of IoT/E will also depend on the selection of the right Packaging Technology. The winner will be the one achieving the following key targets: best electrical and thermal system performance, miniaturization by dense system integration, effective MEMS/Sensors fusion into the systems, manufacturability in high volume at low cost. MEMS/Sensors packaging in low cost molded packages on large manufacturing formats has always been a challenge, whether because of the parameter drift of the sensors caused by the packaging itself or, as in many cases, the molded packaging technology is not compatible to the way MEMS/Sensors are working. Wafer-Level Packaging (WLP), namely Fan-Out WLP (FOWLP) technologies such as eWLB, WLFO, RCP, M-Series and InFO are showing good potential to meet those requirements and offer the envisioned system solutions. FOWLP will grow with CAGR between 50–80% until 2020, forecasted by the leading market research companies in this field. System integration solutions (WLSiP and WL3D) will dominate FOWLP volumes in the future compared to current single die FOWLP packages for mobile communication. The base technology is available and has proven maturity in high volume production, but for dense system integration of MEMS/Sensors, additional advanced building blocks need to be developed and qualified to extend the technology platform. The status and most recent developments on NANIUM's WLFO technology, which is based on Infineon's/Intel's eWLB technology, aiming to overcome the current limits for MEMS/Sensors integration, will be presented in this paper. This will cover the processing of Keep-Out Zones (KOZ) for MEMS/Sensors access to environment in molded wafer-level packages, mold stress relief on dies for MEMS/Sensors die decoupling from internal package stress, thin-film shielding using PVD seed layer as functional layer, and heterogeneous dielectrics stacking, in which different dielectric materials fulfill different functions in the package, including the ability to integrate Microfluidic.

Reliable Via-Middle Copper Through-Silicon Via Technology for 3-D Integration

This paper discusses the key technological aspects of via-middle Cu through-silicon vias (TSVs). The 3-D integration concept and the wafer front and backside process technology for realizing a 5- $\mu \text{m}$ -diameter, 50- $\mu \text{m}$ -deep Si TSV are described. Several options are shown for further, cost-effective, TSV scaling to 3- $\mu \text{m}$ diameter, while maintaining a 50- $\mu \text{m}$ Si thickness. Critical aspects for TSV reliability, such as barrier/liner integrity and Cu pumping, are discussed, and methods for a quantitative study are proposed. Finally, the impact of Cu via-middle TSVs on advanced electronic devices is discussed. A validated model for predicting the stress impact on devices and a method for defining possible keep-out zones are presented.

System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs

Modern 3-D multiprocessor systems-on-chip (MP-SoC) incorporate processing elements (PEs) and memories within die-stacks interconnected using through-silicon vias (TSVs). The resulting power density of these systems necessitates the inclusion of thermal effects in the architecture space exploration stage of the design process. The number and placement of TSVs influences the thermal conductivity in the vertical direction in die-stacks, and consequently these must be considered during thermal analysis. However, the special requirement of keep out zones (KOZs) for TSVs due to mechanical stress considerations complicates the design of the vertical interconnect, potentially impacting its electrical performance as well. This paper presents an integrated methodology that allows for TSV topology exploration to evaluate the best vertical interconnect structure while considering crosstalk, area overheads, and KOZ requirements using an initial system floorplan. After incorporating feedback from the exploration, the resulting vertical interconnect is included within a temperature-power simulation that estimates the thermal profile of the 3-D stack. Within this methodology, a novel power management scheme for 3-D MP-SoCs that considers both temperature as well as positional information and thermal relationships between PEs, while performing dynamic voltage-frequency scaling (DVFS), is introduced. The scheme effectively maintains smooth temperature profiles, decreases fluctuations in voltage-frequency levels, and increases the aggregate frequency of operation at a lower total power dissipation. Further, the scheme is applied to a stack partitioned into voltage islands, where it is shown to match the conventional per-core DVFS schemes in its performance.

Discretized Constrained Attitude Pathfinding and Control for Satellites

A general purpose guidance, navigation, and control algorithm is developed for satellites with three degree-of-freedom rotation maneuverability. The algorithm is capable of meeting multiple pointing constraints autonomously by using a combination of constrained attitude pathfinding and control elements. The unit sphere is discretized into a graph using an icosahedron-based pixelization subroutine. An admissible path between attitude keep-out zones is found with the A* pathfinding algorithm. The trajectory is followed using a rate and torque constrained quaternion feedback controller. The algorithm is capable of running in real time on a low-power flight computer. An embedded version of the algorithm has secured flight opportunities on two student-built three-unit CubeSats. Both sets of mission requirements are satisfied with the same three-unit CubeSat attitude control system, demonstrating the algorithm’s versatility as a general purpose controller. The autonomy provided by the constrained control algorithm enables more complex satellite missions to be performed and decreases the cost of spacecraft subsystems by shifting requirements away from the hardware and onto the control algorithm.

GND Plugs: A Superior Technology to Mitigate TSV-Induced Substrate Noise

Through-silicon vias (TSVs) contribute to substrate noise in 3-D ICs, causing performance degradation of neighboring active devices and requiring keep-out zones. To mitigate TSV-induced substrate noise, we propose a new device, the ground (GND) plug, a TSV-like structure that connects to the ground and extends partially or completely through the substrate. We propose two types of GND plugs: a “front-side” plug, connecting to local interconnect of the same die, and a “back-side” plug, connecting to the GND from the substrate side of the die. We perform comprehensive analyses to evaluate the performance of GND plugs for two substrate types, a high-R bulk and a bulk with epitaxial layer. We compare the GND plug technique with existing noise mitigation techniques: a thicker dielectric liner, a guard ring, and a back-side ground plane. When compared with increased dielectric thickness, the front-side GND plug offers a relative 33% area reduction and allows a significantly reduced keep-out zone. The GND plug offers a more practical noise isolation approach than using a back-side ground plane. Our study demonstrates that the GND plug is a superior technology, effective in mitigating TSV-induced substrate noise by an order of magnitude when compared to the other techniques. The back-side GND plug does not compete with active devices for silicon area yet reduces substrate noise significantly.

Analytical models for the thermal strain and stress induced by annular through-silicon-via (TSV)

Accurate analytical models for the strain and stress in silicon induced by annular Through-silicon-via (TSV) are proposed. Finite element method (FEM) is used for the model verification. It is shown that errors for the strain and stress models are respectively less than 6.6% and 6.8% for various metal and dielectric materials. Based on the analytical model of stress, keep-out-zones (KOZs) are also evaluated for pMOS and nMOS, as the stress is parallel and perpendicular to transistor channel. Annular TSVs with various materials induce KOZs of less than 6.6μm. W exhibits the best thermo-mechanical performance with KOZ=0.