Karatsuba Multiplication Algorithm Research Articles

Signature based Merkle Hash Multiplication algorithm to secure the communication in IoT devices

Great extent of modernization in intelligent device automation and wireless sensor network have encouraged the augmentation of IoTs to interconnect millions of actual devices to the Internet with the help of sensors, actuators and communication technologies. IoT devices with the potential of pervasive sensing and quantifying ability, it becomes an essential segment of the future Internet. The sixth generation (6G) enabled IoT networks are predicted to transform the data sharing and communication for a future of thorough brilliant and sovereign systems. However, secure communication in a sensor network is very difficult and is more amplified by the use of latest 6G IoT technology which is vulnerable to different kinds of attacks due to their limited security features. Existing security systems like RSA and Elliptic curve cryptography which is based on large integer factors and the discrete logarithmic problem is vulnerable to the attack which emerges from quantum computers. The computing capacity of a quantum computer is higher than classical computers. A 30-qubit quantum computer has the equivalent computing capacity as a traditional silicon-based computer computes at 10 teraflops per second. To secure the communication in the present and future IoT network, an enhanced Hash-based Post-Quantum Cryptography (PQC) architecture named Signature-based Merkle Hash Multiplication (SMHM) algorithm is proposed. In the proposed scheme, the Hash-based Merkle signature algorithm is enhanced using the Bernoulli Karatsuba Multiplication algorithm to secure the data storage and communication in IoT devices. The FPGA based proposed model is implemented in the Xilinx ISE14.5 simulator, both Hardware Descriptive Language (HDL) and High-Level Synthesis (HLS) approach is used to calculate the performance metrics which improved 33% frequency, 22% area, power consumption up to 13%, 10% error and 15% delay.

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA.

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over , which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

Instruction Sequences Expressing Multiplication Algorithms

For each function on bit strings, its restriction to bit strings of any given length can be computed by a finite instruction sequence that contains only instructions to set and get the content of Boolean registers, forward jump instructions, and a termination instruction. We describe instruction sequences of this kind that compute the function on bit strings that models multiplication on natural numbers less than $2^N$ with respect to their binary representation by bit strings of length $N$, for a fixed but arbitrary $N > 0$, according to the long multiplication algorithm and the Karatsuba multiplication algorithm. We find among other things that the instruction sequence expressing the former algorithm is longer than the one expressing the latter algorithm only if the length of the bit strings involved is greater than $2^8$. We also go into the use of an instruction sequence with backward jump instructions for expressing the long multiplication algorithm. This leads to an instruction sequence that it is shorter than the other two if the length of the bit strings involved is greater than $2$.

Modified Karatsuba multiplier for key equation solver in RS Code

Finite field arithmetics are often used in linear block codes such as BCH and Reed–Solomon codes and also in cryptographic algorithms. Finite field multipliers play an important role and consume a significant amount of area in VLSI design. This paper presents an improved generalized Karatsuba multiplier. Optimization of the Karatsuba multiplication algorithm can be done by splitting the product terms into two alternative forms and expressing all the terms in the repeated fashion. We have compared the hardware requirement of our proposed multiplier with the original Karatsuba multiplier. The proposed multiplier requires lesser number of additions compared to original Karatsuba multiplier and the overall area is reduced by 53.75% (without reduction) and 52.08% (with reduction). The proposed multiplier is also faster than the original Karatsuba multiplier by 3.63% (without reduction) and 3.91% (with reduction). The proposed modified Karatsuba multiplier is also applied to compute key equation in RS(47, 41) decoder which is applied in intelligent home networking. All the simulation works were done using Xilin14.3 ISE simulator and the multipliers were implemented in Vertex 5 FPGA device family.

Performance Analysis of Karatsuba Multiplication Algorithm for Different Bit Lengths

In computer arithmetic, multiplication is one of the most significant operations. Multiplication is used in many operations such as division, squaring and computing reciprocal. In addition, the efficiency of multiplication is crucial due to the use of digital signal processing applications such as correlation, filtering, frequency analysis and image processing. Karatsuba algorithm is one of the algorithms developed for increasing the efficiency and reducing the cost in order to simplify multiplication. In this study, the performance of Karatsuba algorithm is analyzed in terms of the number of multiplication and the total process time for different bit lengths.

Karatsuba-ZOT Multiplication Algorithm and its Application in Cryptography

The number theory based cryptography algorithms are the most commonly used public-key cryptosystems. One of the fundamental arithmetic operations for such systems is the large integer multiplication. The efficiency of these cryptosystems is directly related to the efficiency of this large integer multiplication operation. Classical multiplication algorithm and Karatsuba multiplication algorithm, and their hybrid, are among the most popular multiplication algorithms used for this purpose. In this paper, we propose a hybrid of Karatsuba and a classical-based multiplication algorithm, enhanced by a new number representation system. The new number representation, known as "Big-Digits”, is used to carry out the sub-multiplication operation in the new multiplication algorithm. Big-Digits has a compact representation with lower Hamming weight. As the result, the number of sub-multiplication operations for the multiplication algorithm that is based on the Big-Digits representation is significantly reduced. Our results show that the proposed multiplication algorithm is significantly faster than the classical, Karasuba and the hybrid of Karatsuba-Classical multiplication algorithms within the implementation domain of the public-key cryptography.