Modified Karatsuba multiplier for key equation solver in RS Code

Abstract

Finite field arithmetics are often used in linear block codes such as BCH and Reed–Solomon codes and also in cryptographic algorithms. Finite field multipliers play an important role and consume a significant amount of area in VLSI design. This paper presents an improved generalized Karatsuba multiplier. Optimization of the Karatsuba multiplication algorithm can be done by splitting the product terms into two alternative forms and expressing all the terms in the repeated fashion. We have compared the hardware requirement of our proposed multiplier with the original Karatsuba multiplier. The proposed multiplier requires lesser number of additions compared to original Karatsuba multiplier and the overall area is reduced by 53.75% (without reduction) and 52.08% (with reduction). The proposed multiplier is also faster than the original Karatsuba multiplier by 3.63% (without reduction) and 3.91% (with reduction). The proposed modified Karatsuba multiplier is also applied to compute key equation in RS(47, 41) decoder which is applied in intelligent home networking. All the simulation works were done using Xilin14.3 ISE simulator and the multipliers were implemented in Vertex 5 FPGA device family.