Junctionless Research Articles

Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate

A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW.

Analytical models for the electric potential, threshold voltage and drain current of long-channel junctionless double-gate transistors

Analytical models for the electric potential, threshold voltage and drain current of long-channel junctionless (JL) double-gate (DG) field-effect transistors (FET) are presented. A regional method is used to solve the Poisson equation under different gate biases, and the electric potential is obtained. With the potential model, an analytical expression for the threshold voltage is achieved. An expression for the drain current is derived from the potential model. The analytical results are compared with simulations, and excellent agreements are observed. The models accurately describe the characteristics of JLDG FETs, and they are very helpful for the design and optimization of devices.

Impact ionization induced dynamic floating body effect in junctionless transistors

Subthreshold Swings, SSs, smaller than theoretical ‘ln(10)kT/q’ are observed in nanowire junctionless (JL) and inversion mode (IM) MuGFETs. The low SS is attributed to the floating body effect in the channel, which is initiated by impact ionization. Comparing with IM devices, decreased drain voltage (Vd) is required for the generation of steep subthreshold slopes in JL devices and the floating body is relatively dynamic. In both JL and IM MuGFETs the floating body effect is suppressed for narrow devices, which indicates this effect is geometry dependent. Moreover, it shows that the short channel JL devices with enhanced electric field can exhibit steep subthreshold slopes at lower Vd. It gives another option to decrease the supply voltage (Vdd) for low power applications of JL devices.

Characteristics of N-Type Planar Junctionless Poly-Si Thin-Film Transistors

In this work, we study the electrical characteristics of planar poly-Si junctionless (JL) thin-film transistors (TFTs) with 10 nm-thick channel and various gate width. The output current of JL devices is drastically larger than that of the control device with an undoped channel, owing to the abundant carriers contained in the channel of the JL devices which tends to reduce both channel and source/drain series resistances. Subthreshold swing of the JL devices is found to be larger than the control ones, owing to the existence of a depletion layer in the channel. Nonetheless, excellent on/off current ratio (>1E+07) is achieved, thanks to the use of the ultra-thin channel.

Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness

N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive and good control over performance variability. From C-V characterization, the ionized dopant concentration in the channel is determined to be around 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and the fixed charge density to be around -6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . The negative fixed charge density is probably related to the segregation of phosphorous species at the oxide/channel interface. We also observed a reverse short-channel effect from the relationship between the threshold voltage and the channel length. One mechanism considering enhanced phosphorous segregation is proposed to explain this finding.

A Continuous Current Model of Accumulation Mode (Junctionless) Cylindrical Surrounding-Gate Nanowire MOSFETs

A continuous current model of accumulation mode or so-called junctionless (JL) cylindrical surrounding-gate Si Nanowire metal-oxide-silicon field effect transistors (MOSFETs) is proposed. The model is based on an approximated solution of Poisson's equation considering both body doping and mobile charge concentrations. It is verified by comparing with three-dimensional simulation results using SILVACO Atlas TCAD which shows good agreement. Without any empirical fitting parameters, the proposed continuous current model of JL SRG MOSFETs is valid for all the operation regions.

Simulation study on short channel double-gate junctionless field-effect transistors

We study the characteristics of short channel double-gate (DG) junctionless (JL) FETs by device simulation. Output I–V characteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed. Distributions of electron concentration, electric field and potential in the body channel region are also analyzed. Comparisons with conventional inversion-mode (IM) FETs, which can demonstrate the advantages of JL FETs, have also been performed.

Performance Comparison Between Bulk and SOI Junctionless Transistors

The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable on/offcurrent ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an on/offcurrent ratio of 105 at W = 10 nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage Vth of the JL bulk FinFET can be easily tuned by varying substrate doping concentration Nsub. The modulation range of Vth as Nsub changes from 1018 to 1019 cm-3, which is around 30%.

Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis

The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ), on current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.

An analytical subthreshold current/swing model for junctionless cylindrical nanowire FETs (JLCNFETs)

Based on the parabolic potential approach (PPA), scaling theory, and drift-diffusion approach (DDA) with effective band gap widening (BGW), we propose an analytical subthreshold current/swing model for junctionless (JL) cylindrical nanowire FETs (JLCNFETs). The work indicates that the electron density of Qm that is induced by the current factor b, minimum central potential Fc, min and equivalent quantum potential FQM is used to determine the subthreshold current/swing for JLCNFET. Unlike the junction-based (JB) cylindrical nanowire FETs (JBCNFETs), the subthreshold current for JLCNFET is not linearly proportional to the silicon diameter, but linearly proportional to the current factor b due to the depletion-typed operation. Apart from short-channel effects (SCEs), the quantum-mechanics effects (QMEs) are included in the model by accounting for the effective BGW, which decreases the electron density in the subthreshold regime and reduces the subthreshold current consequently. Band-to-band tunneling (BTBT) that impacts the subthreshold current is also discussed in the end of the paper. The model explicitly shows how the bulk doping density, drain bias, channel length, oxide thickness, gate workfunction, and silicon film diameter affect the subthreshold current/swing. The model is verified by its calculated results matching well with the data simulated from the three-dimensional device simulator and can be used to investigate the subthreshold current/swing for JLCNFET.

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deplete more electrons than the flat sides or the channel center, when above (local accumulation) and below (local depletion) the flat-band voltage, respectively. On the contrary to the corner effect in the inversion mode (IM) devices, there is no major contribution of corners in the subthreshold current, and therefore, there is no subthreshold device behavior degradation (only one threshold voltage in the system). N-type channel doping levels of 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> , 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> , and 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> were used for quasi-stationary device simulations of JL and AM MOSFETs, and corner effect was studied for 5, 10, and 15 nm wide equilateral triangular Si NW MOSFETs with a 2 nm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate oxide thickness ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0 V; <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> = 300 K). While the local quantum and classical electron density peaks are located in the corner regions above the flat-band voltage, reducing the channel doping and the channel cross-section was found to slightly suppress the normalized total accumulation electron density per unit length, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">acc</sup> /(CW <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ), in strong accumulation regime.

Low-Operating-Voltage Ultrathin Junctionless Poly-Si Thin-Film Transistor Technology for RF Applications

In this letter, for the first time, we experimentally investigate the radio-frequency (RF) characteristics and low-frequency noise (LFN) of n-type planar junctionless (JL) poly-Si thin-film transistors (TFTs). The fabricated JL devices show remarkable dc performance with good current drive and a high on-current/off-current ratio of 8 × 107. Furthermore, with the implementation of an in situ phosphorus-doped channel architecture and a salicide process, the JL device with a channel length of 0.4 μm exhibits a cutoff frequency (ft) of 3.36 GHz and a maximum oscillation frequency (fmax) around 7.37 GHz at a drain bias of 2 V. As far as LFN is concerned, the JL device shows approximately four orders of magnitude lower drain-current noise power spectral density (Sid) over conventional inversion-mode counterparts. These results demonstrate that the JL poly-Si TFT technique is promising for RF modules implemented in system-on-panel applications.

A New Quasi-2-D Threshold Voltage Model for Short-Channel Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs

Based on the quasi-2-D scaling equation, a new threshold voltage model for short-channel junctionless (JL) cylindrical surrounding gate (JLCSG) MOSFETs is developed. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage behavior. The model can also be extendable to its counterpart of junction-based cylindrical surrounding gate (JBCSG) MOSFETs. The model is verified by its calculated results matching well with those of the 3-D numerical simulator and can be easily used to explore the threshold voltage characteristics of JLCSG MOSFETs for its simple formula and computational efficiency.

High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications

In this letter, we demonstrate the usefulness of ultralow-power (ULP) junctionless (JL) MOSFETs in achieving improved analog/RF metrics as compared to nonunderlap and underlap MOSFETs. At a drain current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> ) of 10 μA/μm, JL devices achieve two times higher values of cutoff frequency ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> ) and maximum oscillation frequency ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> ) along with 65% improvement in voltage gain ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> ) in comparison to conventional nonunderlap MOSFETs. ULP JL devices, which do not require source/drain (S/D) profile optimization, can perform comparably to underlap devices, thereby relaxing the stringent process constraints associated with S/D profile optimization in nanoscale devices. The results highlight new opportunities for realizing future ULP analog/RF design with JL transistors.

A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs

Based on the bulk conduction mode of the quasi-2-D scaling theory, an analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation. The model can also be extended to modeling accumulation/inversion operation mode for JL/junction-based double-gate MOSFETs. The model is verified by 2-D device simulations and can be easily used to explore the threshold voltage behavior of the JL double-gate MOSFETs due to its simple formula and computational efficiency.

Junctionless Fabrication on SOI Wafers Using Focused Ion Beam Milling and Al Diffusion

pMOS Junctionless (JL) devices were fabricated on Silicon On Insulator (SOI) substrates using gallium (Ga+) Focused Ion Beam (FIB) milling and Al diffusion, to get Si nanowire with p+ doping, respectively. Furthermore, SiO2 and Pt layers were used as gate dielectric and electrodes (gate, drain and source) of Junctionless transistors, respectively, and also were deposited using Ga+ FIB. Width, length and height dimensions of Si nanowire were about 100~300 nm, 4 μm and 200 nm, respectively. Energy Dispersive X-Ray Spectroscopy (EDS) measurements were carried out to confirm the surface composition of Si nanowire, dielectric and electrodes. In addition, from EDS results, Ga incorporation on Si nanowire surface occurred. This incorporation was from Ga+ FIB with no significant damage on Si nanowire. Drain-source current (Id) x drain source voltage (Vds) measurements of JL transistors were carried out, and indicate that the devices are working, like a gated resistor or JL device, with high Pt source and drain contact resistances, which lead to the distortions of Id x Vds curves. However, these distortions can be reduced using a longer time of contact sintering process and a Si nanowire height lower than 50 nm. Finally, our fabrication method using FIB process steps (Si milling, SiO2 and Pt depositions) and Al diffusion can be used to obtain Junctionless devices.

Drain breakdown voltage: A comparison between junctionless and inversion mode p-channel MOSFETs

A comparative study of the drain breakdown phenomena in junctionless (JL) and inversion mode (IM) p-channel MOSFETs has been investigated experimentally with different VGS, channel widths, and VSUB. In order to explain the dependence of drain breakdown voltages (BVDS) on VGS, 3-D device simulation has been also performed. When the device is turned ON, the BVDS is larger in JL than IM transistors. The BVDS is decreased with the increase of |VGS| in IM transistors but it is increased in JL transistors. When the device is turned OFF, the BVDS is larger in IM than JL transistors. The BVDS is decreased with the increase of channel width for JL and IM transistors. The BVDS is decreased in IM transistor when the back surface state of Si film is changed from the accumulation to the inversion but it is almost constant in JL transistors.

Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications

In this paper, we present the radiofrequency (RF) modeling for gate-all-around (GAA) junctionless (JL) MOSFETs with 30-㎚ channel length. The presented non-quasi-static (NQS) model has included the gate-bias-dependent components of the source and drain (S/D) resistances. RF characteristics of GAA junctionless MOSFETs have been obtained by 3-dimensional (3D) device simulation up to 1 ㎔. The modeling results were verified under bias conditions of linear region (VGS = 1 V, VDS = 0.5 V) and saturation region (VGS = VDS = 1 V). Under these conditions, the root-mean-square (RMS) modeling error of Y₂₂-parameters was calculated to be below 2.4%, which was reduced from a previous NQS modeling error of 10.2%.

70.2: Impact of Gate Oxide Thickness and Channel Length on Junction‐Less Poly‐Si TFTs

AbstractPoly‐Si junctionless (JL) TFTs with various structural parameters were characterized. Owing to the presence of abundant carriers in the channel and elimination of junctions, dramatically increased current drive is achieved with the JL device. Improved control over short‐channel effects and characteristics fluctuation is also achieved with a thinner gate oxide.

A Compact Model of Quantum Electron Density at the Subthreshold Region for Double-Gate Junctionless Transistors

A compact model of quantum electron density at the subthreshold region is derived for junctionless (JL) double-gate (DG) FETs. The proposed quantum model is obtained under two different quantum confinement conditions. One is for a case of a thick channel and a heavily doped channel, where quantum confinement effects (QCEs) are modeled by a 1-D quantum harmonic oscillator. The other is for a case of a thin channel, where QCEs are modeled by the use of a 1-D quantum well surrounded by high potential barriers and an energy correction term coming from the depletion charge. It is shown that, regardless of the channel thickness, the quantum confinement is higher in JL than in inversion-mode (IM) DG FETs. However, for a thin channel, the quantum threshold voltage shift is less severe in JL than in IM DG FETs. The proposed model gives an analytical expression for the threshold voltage shift due to QCEs, which can be used as a quantum correction term for compact modeling.