Junctionless Fabrication on SOI Wafers Using Focused Ion Beam Milling and Al Diffusion

Abstract

pMOS Junctionless (JL) devices were fabricated on Silicon On Insulator (SOI) substrates using gallium (Ga+) Focused Ion Beam (FIB) milling and Al diffusion, to get Si nanowire with p+ doping, respectively. Furthermore, SiO2 and Pt layers were used as gate dielectric and electrodes (gate, drain and source) of Junctionless transistors, respectively, and also were deposited using Ga+ FIB. Width, length and height dimensions of Si nanowire were about 100~300 nm, 4 μm and 200 nm, respectively. Energy Dispersive X-Ray Spectroscopy (EDS) measurements were carried out to confirm the surface composition of Si nanowire, dielectric and electrodes. In addition, from EDS results, Ga incorporation on Si nanowire surface occurred. This incorporation was from Ga+ FIB with no significant damage on Si nanowire. Drain-source current (Id) x drain source voltage (Vds) measurements of JL transistors were carried out, and indicate that the devices are working, like a gated resistor or JL device, with high Pt source and drain contact resistances, which lead to the distortions of Id x Vds curves. However, these distortions can be reduced using a longer time of contact sintering process and a Si nanowire height lower than 50 nm. Finally, our fabrication method using FIB process steps (Si milling, SiO2 and Pt depositions) and Al diffusion can be used to obtain Junctionless devices.