Chip Junction Temperature Research Articles

Theoretical and experimental characterization of heat dissipation in a board-level microelectronic component

In this study, the steady-state heat transfer characteristics of a board-level microelectronic component in natural convection are investigated through numerical modeling and experimental validation. A typical plastic ball grid array (PBGA) package assembled to a piece of printed circuit board (PCB) is considered as the test vehicle. To achieve the goal, a three-dimensional (3D) finite element (FE) modeling technique that utilizes an effective heat conduction FE model together with empirical heat transfer (HT) coefficient correlation models for describing surface heat transfer of the electronic assemblies is applied for theoretical characterization while an infrared thermography-based technique (IRT) that incorporates FE modeling and IR thermography measurement, and a thermal test die measurement (TTDM) technique are applied for experimental validation. To facilitate the IR thermography measurement, the black paint coating technique is applied. The emissivity and optimal thickness of the specific black paint are explored through simple experiments. Besides, the uncertainty in the TTDM for the chip junction temperature measurement is also assessed. By the validated theoretical analysis model, numerical investigation of heat transfer enhancements, such as thermal balls and thermal vias, in the board-level microelectronic component is also accomplished, and eventually, an extensive thermal design guideline is accordingly provided.

A Force-Directed-Based Optimization Scheme for Thermal Placement Design of MCMs

Thermal management becomes exceptionally critical to both the reliability and operation performance of electronic packages, particularly for multichip modules (MCMs), as packaging and power densities continue increase while packaging dimension continues decrease. The underlying goal of the study is to pursue the minimum system temperature design of MCMs containing a number of chips of equal and/or unequal power through the optimal chip placement design. To deal with the thermal design problems, an effective indirect optimization approach that integrates a modified force-directed (FD) thermal model, a finite-element (FE) technique and an exterior penalty method (EPM) is proposed. In the modified FD thermal model, a novel representation of the repulsive and attractive forces is proposed, and the sum of these forces in the design system, representing the total system chip junction temperature, constructs the objective of the optimization problems. Together with some geometry constraints, the constrained optimization problems are formed, and furthermore, transformed into unconstrained optimization problems using an EPM. The solution of the optimization problems is sought through a direct, iterative search scheme with two proposed placement strategies. The alternative goal of the study is to address the feature and feasibility of these two proposed placement strategies for the current problems. The applicability of the proposed optimization approach is demonstrated through several design applications, and their results are extensively compared against the published data. It turns out that the current optimization approach can be very effective and robust in providing thermal optimal design of MCMs with a minimal total chip junction temperature through optimal chip placement

Application of computational fluid dynamics simulation tools for thermal characterization of electronic packages

PurposeIn the semiconductor electronics industry, effective heat removal from the integrated circuits (IC) chip, through the electronic package to the environment is crucial to maintain an allowable junction temperature of the IC chip. Thermal performances of such electronic packages are characterized by package thermal resistance called θ‐JA and are widely used in the electronic industry. Improving thermal performance is numerically predicted using computational fluid dynamics (CFD) technique and experimental tests are carried out to verify the numerical predictions. To provide new/additional data and demonstrate CFD technique for thermal characterization of electronic packages with experimental results.Design/methodology/approachThe thermal performance of electronic packages has been studied using a CFD technique. The finite volume method is a technique used for solving a set of partial differential equations in a domain, using control volume based discretization. A detailed thermal model of an electronic package was created using a CFD tool and validated against the experimental data obtained in a natural convection environment, compliant to JEDEC standards. The thermal performance of the package was evaluated for different die sizes and epoxy molding compounds at different power levels. The use of a heat slug was investigated to identify its effect on heat dissipation for the future generations of IC, which are expected to be smaller in size and to dissipate more power. Free convective flow velocities, detailed temperature and heat flow distributions around the package will also be presented.FindingsThe study demonstrates that applying CFD techniques can provide accurate results on estimating thermal characterization of an electronic package. Predicted device junction temperatures as well as the thermal resistance of packages can be predicted with a good accuracy for different ranges of power levels in natural convection. The numerically estimated die junction temperatures have also been found to be accurate and reliable.Research limitations/implicationsThe analysis is limited to an incompressible fluid. The effect of forced convection is not considered.Practical implicationsNew and additional generated data will be helpful in the design and decision making time of the product to choose a low cost and viable thermal performance solution in the cooling of electronic components at low power.Originality/valueThe electronic package involves multi‐material and applying CFD technique is useful to determine the accurate thermal performance and simple and fast to apply for different conditions/material sets. Predictions of junction‐to‐ambient thermal resistance and device junction temperature values are compared against measurements. Excellent correlation was obtained. The results thus obtained compare well with the experimental results, but the computational effort and time required in the analysis is much small as compared.

On the Thermal Performance Characteristics of Three-Dimensional Multichip Modules

The study explores the thermal performance of three-dimensional (3-D), vertically stacked multi-chip modules (the so-called MCM-V) in natural convection through finite element (FE) modeling and experimental validation. A modified Infrared (IR) thermography-based thermal characterization (IRTTC) technique that integrates a 3-D heat conduction FE modeling and a two-phased IR thermography measurement process is proposed. In contrast to the conventional IRTTC technique (Chen et al. [1]), the technique can improve the resolution of the captured thermal images so as to attain better characterization of the chip junction temperature. The effectiveness of the proposed modified IRTTC technique is confirmed by means of the thermal test die (TTD) measurement. Furthermore, for facilitating subsequent parametric thermal design, a direct FE approach (DFEA) is also introduced. The DFEA simply incorporates existing empirical models for heat transfer (HT) coefficients to describe the surface heat transfer to the ambient through convection and radiation in the proposed heat conduction FE model. Through the modified IRTTC technique and the TTD measurement, the validity of the proposed FE modeling, including the proposed heat conduction FE model and the applied empirical models for HT coefficients, is verified. With the validated FE modeling, four different chip stacking structures of MCM-V packages, including the thick-die-attach, pyramid, cross and dummy-die types, are investigated. In addition, some essential design factors, affecting the thermal performance of the MCM-V, are also extensively explored through parametric FE study. Eventually, an extensive thermal design guideline is accordingly provided.

Prediction of temperature in silicon chip with non‐uniform power: a Lagrangian interpolation approach

This paper describes a generalized method of predicting the temperature distribution of the silicon chip with non‐uniform power dissipation patterns using Lagrangian interpolation function. A simplified heat sink thermal design was modeled to simulate a typical thermal design of microprocessor. Key thermal design parameters investigated are the heat source placement distance and level of heat dissipation. Verification of the proposed method was carried out by comparing the results with FEA predictions. Results of the verification show that the proposed method is reasonably accurate for practical purposes. A successful attempt has been made to predict the junction temperature of silicon chip with non‐uniform power distribution in a simple way.

Integration of Simulation and Response Surface Methods for Thermal Design of Multichip Modules

This paper presents a mathematical expression of the chip junction temperature in terms of chip spatial location and size for effective thermal characterization of ball grid array (BGA) typed multichip modules (MCMs). It is created through the integration of the finite element (FE) analysis and the response surface methods (RSMs) that introduce an approximation of the chip junction temperature in the form of a global response surface. In place of FE simulations, the global response surface is then used to effectively characterize the thermal performance of MCMs, and facilitate the thermal management and the finding of the optimal thermal design of MCMs. To create a set of response data, a rigorous three-dimensional (3D) FE modeling of the MCM package is first established for thermal analysis. The surface loads of the FE model for the heat conduction problems are described by using existing heat transfer (HT) coefficient correlation models. The validity of the proposed FE modeling is substantiated by both the IR thermography-based thermal characterization (IRTTC) approach and the thermal test die measurement based on joint electron device engineering council (JEDEC) specification under a natural convection environment. The uncertainty of the specific power supply applied in the study and the thermal test die measurement is also analyzed. To demonstrate the proposed methodology, two types of MCM thermal design problems are fulfilled, each of which corresponds to a different chip layout. It turns out that the mathematical expression could not only effectively define the relation of the thermal performance and design parameters but also highlight their combinatorial effect.

Thermoelectric cooler application in electronic cooling

This study addresses thermoelectric cooler (TEC) applications in the electronic cooling. The cold side temperature ( T c) and temperature difference between TEC cold and hot sides (Δ T= T h− T c, T h=temperature of hot side of TEC) were used as the parameters. The cooling capacity, junction temperature, coefficient of performance (COP) of TEC and the required heat sink thermal resistance at the TEC hot side were computed. The results indicated that the cooling capacity could be increased as T c increased and Δ T was reduced. The maximum cooling capacity and chip junction temperature obtained were 207 W and 88 °C, respectively. The required heat sink thermal resistance on TEC hot side was 0.054 °C/W. Larger cooling capacity and higher COP could be obtained when the TEC was operated in the enforced regimes (Δ T<0). However, TEC performance was restricted by the T c values and heat sink thermal resistance at the TEC hot side. A microchannel heat sink using water or air as the coolant was demonstrated to meet the low thermal heat sink resistance requirement for TEC operated at maximum cooling capacity conditions.

An effective methodology for thermal characterization of electronic packaging

An effective and novel methodology that integrates infrared (IR) thermography measurement and a three-dimensional (3-D) finite element (FE) model is proposed for thermal characterization of packages in a steady state under a natural convection environment based on JEDEC specification . To perform surface temperature measurement using an IR thermometer, a black paint coating is applied on the surface of packages so as to calibrate the surface radiation. The associated emissivity is approximately assessed using a simple calibration experiment, and an appropriate thickness of the coating is determined. By using a typical 100-lead Thin Quad Flat package (TQFP) as the test vehicle, the proposed methodology is benchmarked by a thermal test die measurement in terms of the junction-to-ambient (J/A) thermal resistance and the chip junction temperature. To demonstrate the accuracy of the benchmarked data from the thermal test die measurement, a corresponding uncertainty analysis is performed. It is found that the worst possible uncertainty in the measured power, based on the specific power supply, is about 0.005 W and that of chip junction temperature measurement is about 0.78/spl deg/C. Additional studies are performed to evaluate the feasibility of the correlation models for convective heat transfer coefficients on typical TQFP packages. It turns out that for a small device such as the TQFP package, these correlation models are fairly reliable.

A power, packaging, and cooling overview of the IBM eServer z900

This paper provides an overview of the power, packaging, and cooling aspects of the IBM eServer z900 design. The semiconductor processor chips must be supported and protected in a mechanical structure that has to provide electrical interconnects while maintaining the chip junction temperature within specified limits. The mechanical structure should be able to withstand shock and vibrations during transportation or events such as earthquakes. The processor chips require electrical power at well-regulated voltages, unaffected by the ac-line voltage and load current fluctuations. The acoustical and electromagnetic noise produced by the hardware must be within the limits set by national regulatory agencies, and the electronic operations must be adequately protected from disruption caused by electromagnetic radiation. For high availability, the power, packaging, and cooling hardware must have redundancy and the ability to be maintained while the system is operating. This paper first overviews the packaging hardware, followed by a description of the first- and second-level packaging, which includes the mother board and the multichip module. Thermal management is discussed from the point of view of both the multichip module and the overall system. Power conversion, management, and distribution are presented next. Finally, the design aspects involved with meeting the requirements of electromagnetic compatibility, acoustics, and immunity to shock, vibration, and earthquakes are discussed.

A Numerical Study of the Thermal Performance of a Tape Ball Grid Array (TBGA) Package

This paper deals with the thermal management of a TBGA chip carrier package. In TBGA packages the backside of the chip is available for heat sink or heat spreader (cover plate) attach. By attaching a heat sink directly to the chip and using a thin layer of high thermal conductivity adhesive, a very low internal thermal resistance can be achieved. The package is attached to an organic card and placed vertically in a channel. A three-dimensional conjugate heat transfer model is used, accounting for conduction and radiation in the package and card and convection in the surrounding air. A simplified turbulence model is developed to predict temperatures in the low Re turbulence regime. A parametric study is performed to evaluate the effects of card design, air velocities, interconnect thermal conductivities and thermal radiation on the chip junction temperatures. An experimental study was also conducted to verify the model. Even though the geometry is highly complex due to the multilayer construction of the module and the card, agreement between the model and the experimental measurement is excellent. It was shown that radiation heat transfer can be an equally significant mode as convection in the natural convection regime. [S1043-7398(00)01302-5]

THERMAL DISSIPATION CHARACTERISTICS OF A TAPE AUTOMATED BONDING ELECTRONIC PACKAGE

Thermal measurements play a very important role in the successful design and thermal management of electronic packages. Accurate measurements of temperature distribution under different conditions are necessary to characterize the thermal resistance of electronic packages from the chip junction to the cooling sink. This paper deals with the effects of power dissipation, air velocity and ambient temperature on the thermal performance of a tape automated bonding (TAB) package. In this study, the characteristics of junction temperature (TJ), junction to ambient thermal resistance (θJ-A), junction to case thermal resistance (θJ-C), and case to ambient thermal resistance (θC-A) are investigated in detail. The package was placed in a custom-designed low speed wind tunnel which allows the air velocity to be varied between 0.5 m/s and 5 m/s. Package surface temperatures were measured using infrared thermography, while chip junction temperatures were indirectly obtained using the Electrical Test Method (ETM) in accordance to Military Standard 883. The experimental results show that for the TAB package, air velocity significantly affects θC-A and θJ-A but has negligible effect on θJ-C· In contrast, θJ-C was found to be dependent on power dissipation. In addition, the ambient temperature was found to have a strong effect on the thermal performance of the TAB package. For the tested TAB package, it was noted that the inner lead temperatures are higher than that of the chip epoxy surface.

A feasibility study for the fabrication of planar silicon multichip modules using electron beam lithography for precise location and interconnection of chips : Andy Hopperet al. IEEE Trans. Compon. Hybrids mfg Technol.15, 97 (1992)

The study attempts to seek the optimal thermal design of planar multichip module (MCMs) under natural convection through optimal chip placement design. To attain the goal, a sequential metamodeling-based optimization approach is introduced. This approach incorporates a response surface methodology (RSM)-based design of experiment (DOE), three-dimensional (3D) thermal finite element analysis (FEA) and an updating scheme. Essentially, the RSM is used to construct, via quadratic polynomial approximation, the global RS of the chip junction temperature in terms of design variables. For speeding up the DOE and the solution of the optimization, several dynamic experimental design strategies using move limits and different proposed sampling techniques are introduced. The feasibility of the strategies is demonstrated, and their solution accuracy and efficiency are also compared with each other. By the explicit RS-based performance function together with geometry constraints, a constrained thermal optimization subproblem is formed. The optimum of the subspace optimization is sought, which is considered as the nominal starting point of next iteration. The iterative process continues with a new defined design subspace and factorial design plan until convergence is attained. The applicability of the proposed design optimization technique is demonstrated through several design case studies involving various planar MCMs.

Development and analysis of an automated test system for the thermal characterization of IC packaging technologies

The development of an automated test system for the thermal characterization of IC packages is reported. A range of thermal test chips which have also been developed is described. The thermal test system is discussed in detail in terms of the temperature sensor calibration algorithm and the error budget associated with junction-to-case thermal resistance measurements in an oven environment. A detailed discussion of the experimental errors and uncertainties is presented. A figure of +or-4% has been obtained for both the accuracy and repeatability of an oven-based junction-to-case thermal resistance test method. This is shown to compare favorably with the performance of a temperature controlled heat sink system. By comparison with infrared thermal imaging, the measurement of the average chip junction temperature is shown to provide an accurate thermal resistance figure for conventional IC package structures. IC packages used to demonstrate the application of the test system and test chips to thermal characterization include DIPs, PGAs, and chip carriers. >

Design and Development of a 68-Lead Nonhermetic Leaded Chip Carrier

The design and development of a 68-lead nonhermetic leaded chip carrier (CC) suitable for Packaging a high-speed bipolar gate array device with several watts of power dissipation are covered. This CC was designed to make use of thin-film hybrid assembly technology with a package outline generally consistent with the JEDEC Leaded Type A Standards. The CC is compatable with different silicon integrated circuit (SIC) attachment methods and provides high thermal performance. The CC was constructed using titanium/palladium/gold thin-film circuitry on 99.5 percent alumina, with package leads attached to the thin-film circuit by thermal compression bonding. The assembly of the silicon device to the ceramic involved epoxy die bonding and thermosonic gold wire bonding. The majority of the work on the CC was performed with a thermal test chip. The assembled CC device was coated with RTV and an epoxy for environmental protection, and the external leads were formed around a plastic insert to meet the JEDEC outline. An aluminum heat spreader was attached to the back surface of the ceramic. A surface solder method for the attachment of the CC to a printed wiring board (PWB) was developed. The fatigue resistance of the solder joints was demonstrated to be adequate. Temperature rise versus power measurements were made on CC's with and without heat spreaders and on a CC/PWB assembly. From the data, the thermal · resistances of the packages were determined and used in defining a simple model of the CC package and a CC/PWB package combination. Depending on the environment of the CC device, a forced air velocity range was determined to maintain chip junction temperatures below allowed maximums. It was determined that the thermal performance of the CC packaged device would be satisfactory for use with a 2-W chip in a moderate forced air environment.

Steady-state junction temperatures of semiconductor chips

The temperature drop between a transistor junction and the base of a silicon chip is dependent upon the power to be dissipated as well as the geometry of the device. This problem in three-dimensional heat conduction is analytically solved for boundary conditions which approximate a set of operating conditions. Nondimensional curves and examples summarizing typical solutions have been included to illustrate problem solving techniques.