Junction Formation Technology Research Articles

Ge-on-insulator tunneling FET with abrupt source junction formed by utilizing snowplow effect of NiGe

Tunneling field-effect transistors (TFETs) attract much attention for use in realizing next-generation low-power processors. In particular, Ge-on-insulator (GOI) TFETs are expected to realize low power operation with a high on-current/off-current (Ion/Ioff) ratio, owing to their narrow bandgap. Here, to improve the performance of GOI-TFETs, a source junction with a high doping concentration and an abrupt impurity profile is essential. In this study, a snowplow effect of NiGe combined with low-energy BF2+ implantation has been investigated to realize an abrupt p+/n Ge junction for GOI n-channel TFETs. By optimizing the Ni thickness to form NiGe (thickness: 4 nm), an abrupt junction with a B profile abruptness of ∼5 nm/dec has been realized with a high doping concentration of around 1021 cm−3. The operation of GOI n-TFETs with this source junction having the abrupt B profile has been demonstrated, and the improvement of TFET properties such as the Ion/Ioff ratio from 311 to 743 and the subthreshold slope from 368 to 239 mV/dec has been observed. This junction formation technology is attractive for enhancing the TFET performance.

(Invited) Low Power Tunneling FET Technologies Using Ge/III-V Materials

The critical issues, technical challenges and viable technologies of tunneling FETs (TFET) using III-V semiconductors and Ge are addressed in this paper. Device engineering indispensable in improving the performance of TFETs is summarized with emphasis on the source junction formation technology. The fabrication and the electrical characteristics of TFETs using InGaAs bulk and quantum well (QW) homo-junctions, GaAsSb/InGaAs type-II hetero-junctions, Ge homo junctions and Ge/strained SOI type-II hetero-junction are presented as viable examples.

Electron holography analysis of a shallow junction for planar-bulk metal-oxide-semiconductor field-effect transistors approaching the scaling limit

We investigated electrostatic potential distributions in source∕drain extensions (SDEs) in metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated using state-of-the-art junction formation technology. We first demonstrate that electron holography can directly reveal potential distribution in scaled MOSFETs when specimen preparation artifacts are reduced, which we did by using back side low-energy Ar ion milling. Second, we examine the potential distributions in SDEs in a scaled (30-nm-gate-length) MOSFET fabricated by using a combination of cluster B implantation, millisecond annealing, and multihalo implantation. The results show that these junction formation technologies enable fabrication of very abrupt and shallow (10-nm-deep) SDE junctions. In addition, our experimental analysis, in conjunction with a Monte Carlo doping-process simulation, indicates that B channeling along the ⟨110⟩ direction of the Si substrate during the implantation process significantly blurs the SD junction profiles and that multihalo implantation can increase junction abruptness. Third, we show that our experimental results describe well the roll-off characteristics of the MOSFETs.

Ultra-Shallow Junction Formation Technology from the 130 to the 45 nm node

ABSTRACTOne of the main materials challenges of the 130 nm silicon technology node was the need to find a processing solution to the anomalous diffusion behavior of ion-implanted dopants known from three decades of research. Reduction of implantation energy no longer proved sufficient when trying to reduce source/drain extension junction depth, increase abruptness, and limit sheet resistance. Spike-annealing, a new process in which ion implanted silicon could be heated rapidly to temperatures required for dopant activation and then cooled down without dwelling at temperature, adequately addressed the scaling requirements of this node. The resulting junctions achieved high dopant concentration values very close to the surface while limiting junction depth. However, this increased the propensity for dopant migration to overlying layers associated with the source/drain spacer. Loss of device performance due to this and other phenomena became a strong motivating factor for further materials research in order to sustain progress through the 130 nm and 90 nm nodes. Complex interactions between various layers have been understood and the resulting developments in spacer materials have enabled high performance devices. The requirements of the 65 and 45 nm nodes stretch spike-annealing to its limit and newer Ultra-High Temperature anneals must be considered.

HgCdTe long-wavelength infrared photovoltaic detectors fabricated using plasma-induced junction formation technology

A long-wavelength infrared (LWIR) HgCdTe photodiode fabrication process has been developed based on reactive ion etching (RIE) plasma-induced p-to-n type conversion for junction formation. The process has been successfully applied to produce devices using both vacancy-doped and gold-doped liquid phase epitaxy (LPE)-grown p-type HgCdTe material with a cut-off wavelength of 10 µm at 77 K. The fabrication procedure is outlined and results are presented on completed devices that indicate the effect of variations in processing parameters. The fabricated devices have been characterized by measurements of the diode dark I-V characteristic over the temperature range 20–200 K, as well as by spectral responsivity measurements. Analysis of the device I-V data, variable area data, and modeling of diode dark current mechanisms indicates that gold-doped material results in higher performing devices compared to vacancy-doped material. Device performance is found to be strongly affected by trap-assisted tunneling currents and surface leakage currents at zero bias. Nonoptimum surface passivation is likely to be the major factor limiting performance at this early stage of device technology development.

The wet-topotaxial process of junction formation and surface treatments of Cu 2S–CdS thin-film solar cells

The particular properties of Cu 2S–CdS heterojunctions are revealed. The effects of lattice mismatch on epitaxy as well as wet- and dry-topotaxy are discussed and preconditions for successful application of topotaxy are elaborated. The influence of surface treatments of the cells and of additional semiconducting or metallic layers of monolayer-range thicknesses at the surface is demonstrated. The junction formation technology and the surface treatments appear to be relevant also to other photovoltaic devices.

Ultra-shallow junction with elevated SiGe source/drain fabricated by laser-induced atomic layer doping

A novel structure of NMOSFET with elevated SiGe source/drain region and ultra-shallow source/drain extension region is described. A new ultra-shallow junction formation technology, which is based on a damage-free process for replacing low energy ion implantation, is realised using ultra-high vacuum chemical vapour deposition and excimer laser annealing.

HgCdTe photovoltaic detectors fabricated using a new junction formation technology

The current–voltage characteristics measured over a wide temperature range are reported for HgCdTe mid-wavelength infrared n-on-p photodiodes fabricated using a novel junction formation technology. The planar homojunction device junctions were formed on LPE grown vacancy doped HgCdTe using a reactive ion etching (RIE) plasma induced conversion process. The zero bias dynamic resistance–junction area product, RoA, was 4.6×107Ωcm2 at 80K and is comparable to the best planar diodes reported using conventional ion implantation junction formation technology. Arrhenius plots of RoA exhibit an activation energy equal to the bandgap, Eg, and show that the diodes are diffusion limited for temperatures ≥135K. A series of temperature dependent 1/f noise measurements were performed, indicating that the activation energy for 1/f noise in the region where the diodes are diffusion limited is 0.7Eg. Energies close to this value have previously been associated with Hg vacancies in HgCdTe. These results are similar to those obtained from high quality HgCdTe photodiodes fabricated using mature ion implantation technology. However, the plasma based technology used in this work is significantly less complex and does not require any high temperature annealing steps.

Characterisation of dark current in novel Hg 1− xCd xTe mid-wavelength infrared photovoltaic detectors based on n-on-p junctions formed by plasma-induced type conversion

This paper reports initial characterisation results for planar mid-wavelength infrared (MWIR) photodiodes fabricated using a novel reactive ion plasma-induced n-on-p junction formation technology on vacancy-doped p-type HgCdTe grown by LPE on CdZnTe substrates. The junction is formed without the need for post-implant annealing typically required by ion implantation junction formation techniques to repair damage or to move the junction away from damaged regions. The dark current and dynamic resistance, R d, of the fabricated photodiodes have been characterised as a function of temperature. At 80 K, the zero-bias dynamic resistance–junction area product ( R 0 A) of the diodes is 4.6×10 7 Ω cm 2, with the devices being diffusion limited down to ∼135 K. Dynamic resistance has been measured for temperatures between 80 and 195 K and biases between −200 and +150 mV. Modelling of the observed dark current has been undertaken using three distinct mechanisms, diffusion, generation–recombination, and trap-assisted tunnelling. The results show that the plasma-induced junction formation technique can produce high-performance planar HgCdTe photodiodes. The dark current mechanisms found in these devices are similar to those found in diodes formed using conventional ion implantation techniques.

HgCdTe mid-wavelength IR photovoltaic detectors fabricated using plasma induced junction technology

Preliminary characterization results are presented for mid-wave infrared (MWIR) mercury cadmium telluride n-on-p photodiodes fabricated using a plasma induced type conversion junction formation technology. The diodes have been fabricated on three different vacancy doped p-type epitaxial starting materials, grown by liquid phase epitaxy (LPE) on CdZnTe, LPE on sapphire, and P/p isotype heterojunction material grown by molecular beam epitaxy (MBE) on CdZnTe. All materials had CdTe mole fraction in the active region of the device of ∼0.3. The process uses a H2/CH4 plasma generated in a parallel plate reactive ion etching (RIE) system to type convert the p-type material to n-type. The process is different from previously reported type conversion techniques in that it does not require a high temperature anneal, does not expose the junction at the surface to atmosphere after formation, and requires significantly fewer process steps than other planar processes. Homojunction devices fabricated using this process exhibit R0A values >107 Ω·cm2 at 80 K. The R0A is diffusion limited for temperatures >∼135 K. Results for responsivity, bias dependence of dynamic resistance — junction area product and 1/f noise show that the resulting diodes are comparable to the best planar diodes reported in the literature.

Arsenic Ion‐Implanted Shallow Junction

Shallow junction formation technology by arsenic ion implantation is evaluated from the viewpoint of practical application to the coming VLSI's. Carrier profile, residual defect profile, and electrical characteristics are examined as functions of acceleration energy, dose, annealing conditions, and surface oxide thickness. The carrier profile is determined mainly by both arsenic ion amount in the substrate layer and annealing conditions. The residual defect profile is determined by implantation energy and surface oxide thickness. It is necessary to implant arsenic ions shallower than the resulting carrier profile, to obtain arsenic ion‐implanted junctions with acceptable electrical characteristics. A junction diode, with junction depth as shallow as 0.16 μm is fabricated according to this principle, and is ascertained to have acceptable electrical characteristics.